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Chapter 1

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Chapter 1

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  1. Chapter 1 Introduction

  2. Contents • Overview of VLSI design methodology • VLSI design flow • Design hierarchy • Concept of regularity, Modularity, and Locality • VLSI design style • Design quality • Package technology • Computer aided design technology

  3. What is VLSI? • Very Large Scale Integration • design/manufacturing of extremely small, complex circuitry using modified semiconductor material • integrated circuit (IC) may contain millions of transistors, each a few mm in size • applications wide ranging: most electronic logic devices

  4. Origins of VLSI • Much development motivated by WWII need for improved electronics, especially for radar • 1940 - Russell (Bell Laboratories) - first pn junction • 1948 - Shockley, Bardeen, Brattain (Bell Laboratories) - first transistor • 1956 Nobel Physics Prize • Late 1950s - purification of Si advances to acceptable levels for use in electronics • 1958 - Seymour Cray (Control Data Corporation) - first transistorized computer - CDC 1604

  5. Origins of VLSI • 1959 - Jack St. Claire Kilby (Texas Instruments) - first integrated circuit - 10 components on 9 mm2 • 1959 - Robert Norton Noyce (founder, Fairchild Semiconductor) - improved integrated circuit • 1968 - Noyce, Gordon E. Moore found Intel • 1971 - Ted Hoff (Intel) - first microprocessor (4004) - 2300 transistors on 9 mm2 • Since then - continued improvement in technology has allowed for increased performance as predicted by Moore’s Law

  6. Moore’s Law • Moore's law is the observation that, over the history of computing hardware, the number of transistors on integrated circuits doubles approximately every two years

  7. Topic complexity

  8. VLSI design styles

  9. Full-custom/VLSI • All layers are optimized for a system’s particular digital implementation • Placing transistors • Sizing transistors • Routing wires • Benefits • Excellent performance, small size, low power • Drawbacks • High NRE cost, long time-to-market

  10. Semi-custom • Lower layers are fully or partially built • Designers are left with routing of wires and maybe placing some blocks • Benefits • Optimum performance, good size, less NRE cost than a full-custom implementation • Drawbacks • Performance is limited up to certain extent

  11. Technology windows

  12. The Y chart

  13. Simplified design flow

  14. Design hierarchy • The use of hierarchy, or divide and conquer technique involves dividing a module into sub- modules and then repeating this operation on the sub-modules until the complexity of the smaller parts becomes manageable • For example a structural decomposition of a CMOS four-bit adder into its components can be taken • The adder can be decomposed progressively into one- bit adders, separate carry and sum circuits, and finally, into individual logic gates

  15. Design hierarchy

  16. Concepts of Regularity • Regularity means that the hierarchical decomposition of a large system should result in not only simple, but also similar blocks, as much as possible • Regularity can exist at all levels of abstraction: At the transistor level, uniformly sized transistors simplify the design • If the designer has a small library of well-defined and well-characterized basic building blocks, a number of different functions can be constructed by using this principle • Regularity usually reduces the number of different modules that need to be designed and verified, at all levels of abstraction

  17. Example of regularity

  18. Concepts of Modularity • Modularity in design means that the various functional blocks which make up the larger system must have well-defined functions and interfaces • Modularity allows that each block or module can be designed relatively independently from each other, since there is no ambiguity about the function and the signal interface of these blocks • All of the blocks can be combined with ease at the end of the design process, to form the large system

  19. Concepts of Modularity • The concept of modularity enables the parallelization of the design process • It also allows the use of generic modules in various designs - the well-defined functionality and signal interface allow plug-and-play design

  20. Concepts of Locality • By defining well-characterized interfaces for each module in the system, we effectively ensure that the internals of each module become unimportant to the exterior modules • Internal details remain at the local level • The concept of locality also ensures that connections are mostly between neighboring modules, avoiding long-distance connections as much as possible • This last point is extremely important for avoiding excessive interconnect delays

  21. Concepts of Locality • Time-critical operations should be performed locally, without the need to access distant modules or signals • If necessary, the replication of some logic may solve this problem in large system architectures

  22. VLSI design styles • Several design styles can be considered for chip implementation of specified algorithms or logic functions • Each design style has its own merits and shortcomings, and thus a proper choice has to be made by designers in order to provide the functionality at low cost • Some of them are • Field Programmable Gate Array (FPGA) • Gate Array Design • Standard-Cells Based Design • Full Custom Design

  23. Field Programmable Gate Array (FPGA) • Logic gates with programmable interconnects • I/O buffers, configurable logic blocks (CLBs) and programmable interconnect structures • Requires no process steps for logic realization • For fast prototyping and small-volume ASIC production (short turn-around time) • Design flow of FPGA: • Behavioral description of its functionality • Technology-mapped into circuits or logic cells • Assigns logic cells to FPGA CLBs and determines the routing pattern

  24. Field Programmable Gate Array (FPGA) • Configurable logic blocks (CLBs) • Independent combinational function generators (memory look-up table) • Clock signal terminal • User-programmable multiplexers • Flip-flops • Programmable interconnect • Six pass transistors per switch matrix interconnect point • Accomplished by data in RAM cells

  25. Architecture of FPGA

  26. Gate array design • Uncommitted transistors separated by routing channels • Circuit implementation: • 1st phase: generic masks for uncommitted transistors on each GA chip (stored) • 2nd phase: Customization by (multiple) metal fabrication process • Ranks second after FPGA with a turn-around time of a few days • Chip utilization factor is higher than that of the FPGA

  27. Gate array design

  28. Standard-cell based design • Commonly used logics are developed, characterized and stored in a standard cell library • Cell library includes: • Delay time versus load capacitance • Circuit simulation model • Timing simulation model • Fault simulation model • Cell data for place-and-route • Mask data

  29. Standard-cell based design • Standard cell arrangement: • Fixed cell height • Parallel power and ground rails • Input and output pins are located on the upper and lower boundaries • Cells are placed side by side in standard-cell based design • The required logic circuits are realized using the cells in the library

  30. Design quality • There are few widely accepted metrics used to measure the quality of design • Testability • Yield and manufacturability • Reliability • Technology updateability

  31. Testability • Time and effort for chip test increase exponentially with design complexity • The test task requires • Generation of good test vectors • Availability of reliable test fixture at speed • Design of testable chip

  32. Yield and manufacturability • The ratio of good tested chips to total tested chips • Functionality yield: • Testing the chips at lower speed • Identify problems of shorts, opens and leakage current • Detect logic and circuit design failure • Parametric yield • Test at the required speed • Delay testing is performed at this stage • Consider manufacturability of the chip in the design phase

  33. Reliability • Depends on the design and process conditions • Reliability problems: • Electrostatic discharge (ESD) and electrical overstress (EOS) • Electromigration • Latch-up in CMOS I/O and internal circuits • Hot-carrier induced aging • Oxide breakdown • Single event upset • Power and ground bouncing • On-chip noise and crosstalk

  34. Technology updateability • Be technology-updated to new design rules • Fast migration to new process technology • Silicon compilation: generate physical layout from high-level specifications

  35. Packaging technology • Packaging for integrated circuits • Proper packaging technology is critical to the success of the chip development • Package issues have to be taken into consideration in early stages of chip development • Ensure sufficient design margins to accommodate the parasitic of the package

  36. Packaging technology • Important packaging concerns: • Hermetic seals to prevent the penetration of moisture • Thermal conductivity • Thermal expansion coefficient • Pin density • Parasitic inductance and capacitance • α-particle protection • Cost

  37. Packaging technology • Types of packaging technology • Classified by the method used to solder the package on the printed PCB • Pin-through-hole (PTH) • Surface-mounted technology (SMT)

  38. Packaging types • Dual in-line packages (DIP) • Advantage of low cost • Not applicable for high-speed operations due to the inductance of the bond wires • Maximum pin count is typically limited to 64 • Pin grid array (PGA) packages • Offers a higher pin count (several hundreds) • High thermal conductivity especially with a passive or active heat sink • Requires large PCB area • Cost is higher than DIP

  39. Packaging types • Chip carrier packages (CCP) • Leadless chip carrier: • Chip mounted on PCB directly • Supports higher pin count • Problem with difference in thermal coefficient • Leaded chip carrier: • Quad flat packages (QFP) • Similar to leaded chip carrier with leads extending outward

  40. Packaging types • Multi-chip modules (MCM) • Used for very high performance in special applications • Multiple chips are assembled on a common substrate in a single package • A large number of critical interconnects among the chips are made within the package • Important features: • Significant reduction in the overall system size • Reduced package lead counts • Faster operation allowed • Higher implementation cost

  41. Computer aided design technology • Categories of CAD tools for VLSI chip design • Synthesis tools: • High-level synthesis tools with hardware description language • Address automation of the design phase in the top level • Layout tools: • Floorplanning • Place-and-route • Module generation

  42. Computer aided design technology • Simulation and verification tools • Behavior simulation • Logic level simulation • A number of test vectors are applied • Verify logic functionality • Timing level simulation • Circuit-level simulation • Determine nominal and worst-case delays • High computational cost