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Chapter 1

Chapter 1. Performance & Technology Trends. Read Sections 1.5, 1.6, and 1.8. Section 1.5: The Power Wall. Power Trends. Clock rates hit a “power wall”. In CMOS IC technology. × 1000. × 30. 5V → 1V. The power wall. Performance was always improved by increasing frequency (up to 2004)

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Chapter 1

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  1. Chapter 1 Performance & Technology Trends Read Sections 1.5, 1.6, and 1.8

  2. Section 1.5: The Power Wall Chapter 1 — Computer Abstractions and Technology — 2

  3. Power Trends • Clock rates hit a “power wall” • In CMOS IC technology ×1000 ×30 5V → 1V Chapter 1 — Computer Abstractions and Technology — 3

  4. The power wall • Performance was always improved by increasing frequency (up to 2004) • However by 2006, companies could not reduce generated power and remove more heat • Hence performance improvement could not be achieved by increasing frequency because of the increased power generated >>>>> THE POWER WALL • How else can we improve performance? Chapter 1 — Computer Abstractions and Technology — 4

  5. Read Section 1.6: The Sea Change The Switch to Multiprocessors Chapter 1 — Computer Abstractions and Technology — 5

  6. Uniprocessor Performance Uniprocessor performance is constrained by power, instruction-level parallelism, memory latency Chapter 1 — Computer Abstractions and Technology — 6

  7. A Sea Change is at Hand • The power challenge has forced a change in the design of microprocessors • Since 2002 the rate of improvement in the response time of programs on desktop computers has slowed from a factor of 1.5 per year to less than a factor of 1.2 per year • As of 2006 all desktop and server companies are shipping microprocessors with multiple processors – cores – per chip • Plan is to double the number of cores per chip per generation (about every two years) Plan not followed!!

  8. 8 Multicore microprocessors • Require explicitly parallel programming • In single core microprocessors, hardware implemented instruction level parallelism to execute multiple instructions IN PARALLEL • Instruction level parallelism is hidden from the programmer • Parallel programming is hard (harder) to do. Involves: • Programming for performance • Load balancing • Optimizing communication and synchronization With the introduction of multicore microprocessors, The Free Lunch Era Ended !!!

  9. Read Section 1.8: Pitfalls and Fallacies

  10. Pitfalls and Fallacies • Pitfalls: Easily made mistakes • Fallacies: • Errors • Myths • …

  11. Pitfall: Amdahl’s Law • Pitfall: Improving an aspect of a computer and expecting a proportional improvement in overall performance • Example: multiply operations account for 80 seconds of a 100 seconds run time of a program • How much improvement in multiply performance to get theprogram to run 5 times faster (i.e. in {100/5} = 20s)? • Can’t be done!

  12. Amdahl’s Law Best Speedupoverall you could ever hope to do: fraction enhanced ExTimeold ExTimenew

  13. Amdahl’s Law example • New CPU 10X faster • I/O bound server, so 60% time waiting for I/O • Apparently, its human nature is to be attracted by 10X faster, vs. keeping in perspective that it is just 1.56X faster 13

  14. Amdahl’s Law example:Make the common case fast • Fraction = 0.1, Speedup = 10 • Fraction = 0.9, Speedup = 10 14

  15. Pitfall: MIPS as a Performance Metric • MIPS: Millions of Instructions Per Second • Doesn’t account for • Differences in ISAs between computers • Differences in complexity between instructions 15

  16. Pitfall: MIPS as a Performance Metric (cont.) • How should MIPS be computed? • It is not the maximum theoretical MIPS quoted by the manufacturer. • CPI varies between programs on a given CPU

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