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Motivation

Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning Lithography Kwangok Jeong and Andrew B. Kahng VLSI CAD LABORATORY UC San Diego http://vlsicad.ucsd.edu/ Research supported by STARC ASP-DAC Session 5B, January 21, 2009. Motivation.

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Motivation

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  1. Timing Analysis and Optimization Implications of Bimodal CD Distribution in Double Patterning LithographyKwangok Jeong and Andrew B. Kahng VLSI CAD LABORATORY UC San Diego http://vlsicad.ucsd.edu/ Research supported by STARCASP-DAC Session 5B, January 21, 2009

  2. Motivation • Single exposure lithography • All shapes printed by one exposure • Adjacent identical features have same mean CD (critical dimension), and spatially correlated CD variations • Double patterning lithography (DPL) • Shapes are decomposed and printed in two exposures • Adjacent features can have different mean CD, and uncorrelated CD variations  New set of ‘bimodal’ challenges for timing analysis and optimization

  3. DPL Approaches • Print lines • Misalignment  No CD difference between two adjacent lines • CD control is key factor • Print edges • Exposure difference  No CD difference between two adjacent lines • Overlay control is key factor 2nd Exp. 1st Exp. Resist 2nd Etch 1st Exp./Etch Resist Hardmask Poly Poly CD variation w/o misalignment CD variation w/o misalignment 1st Exp. 1st Exp. & Etch 2nd Exp. 1st Exp. 1st Exp./Etch 2nd Etch 2nd Exp. 2nd Exp. CD variation w/ misalignment CD variation w/ misalignment Final patterns Final patterns

  4. Bimodal CD Distribution • TwoCD distributions and Two different colorings  Twodifferent timings • This Research • Assess potential impact of bimodal CD distribution on timing analysis and guardbanding • Cell delay and power, path delay, clock skew, path timing slack • Seek potential solutions to minimize the impact of bimodal CD distribution M12-type cell M21-type cell Gates from CD group1 Gates from CD group2

  5. 16-stage 2-types 2-types 2-types 2-types Impact on Path Delay Variation • Simulation setup • 45nm PTM, Typical corner (TT), 1.0V, 25 °C • 16 stages of 45nm INVX4 (Nangate Open Cell Library) • Each cell can have two different colorings • Each color (Mask 1 or 2) can have two different process results (Min or Max) • Simulation results • Mean and sigma of a long inverter chain (16 stages)over all process corners (Min and Max combinations) • Alternately-colored paths smaller path delay variation Covariance worsens path delay variation

  6. Impact on Timing Slack (Analysis) • Timing slack calculation • Timing slack: • Timing slack variation: • Clock skew • Especially, clock skew from uncorrelated launching and capturing clock paths are the major source of timing slack variation. • Example Large correlation is better for timing slack Data (10 – 5 = 5ns) BC Clock (10 – 5 = 5ns) Data (10  2 = 8~12ns) Worst slack = 5  5 = 0ns Clock (10  2 = 8~12ns) Data (10 + 5 = 15ns) WC Worst slack = min(clock) – max(data) = 8  12 =  4ns Clock (10 + 5 = 15ns) Worst slack = 15  15 = 0ns • Worst slack in DPL • Small delay variation • but large negative slack (b) Worst slack in single exp. Large delay variation but zero slack

  7. Impact on Timing Slack (Simulation Setup) • Testcase • AES from Opencores, Nangate 45nm library, PTM 45nm • Extracted critical path • Exhaustive tests (4 x 254) not feasible, so we fix the data path coloring. Data path: 30 stages Clock launch: 14 stages Clock capture: 14 stages

  8. Impact on Timing Slack (Simulation Results) • Clock skew • Even for the zero mean difference case, clock skew exists and increases with mean difference • Pooled unimodal can not distinguish this clock skew • Timing slack • Originally zero slack turns out to have significant negative slack • Pooled unimodal shows very pessimistic slack 53ps 22ps Cases 1, 2, 5

  9. Possible Solutions for Timing Optimization • Self-compensation • Alternative coloring of timing paths  reduce variation • Same coloring sequence for clock network  reduce clock skew  But: restricted coloring can increase coloring conflicts • Solutions for coloring conflicts • Candidate1: large sized cells to prevent conflicts between cells • Candidate2: Placement legalization after coloring (like UCSD *Corr) dpb 2dpb  Resmin 2dpb  Resmin > Resmin Coloring-fixed cells Coloring conflict dpb: distance from poly center to cell boundary Resmin: minimum resolution (a) Conflict (b) No conflict Logical connection (a) Original placement (b) Alternative coloring (c) Conflict Removal

  10. Self-Compensation Is Not Enough • Self-compensation in path coloring reduces delay variation, but bimodal CD impact is still significant Better, but can still have timing violations

  11. BEOL Compensation of Measured FEOL CD • UCSD: “Design-Aware Process Adaptation” • FEOL metrology  intentional BEOL CD biasing • DPL allows wire segments in different masks to change CD independently • Color interconnects differently for different CD groups • F-factor = (in)flexibility factor for interconnect coloring, e.g., F=1, • All wire segments connected to CD_group1 gates must be in INT_MASK1 • All wire segments connected to CD_group2 gates must be in INT_MASK2

  12. Compensation with BEOL Biasing • Small CD gates  thick interconnect (large cap.) • Large CD gates  thin interconnect (small cap.) • Example for F=0.8 (80% of interconnects colored according to the gate CD groups) meet timing Change metal/ILD thickness?

  13. Conclusions • Analytical and empirical assessments of DPL potential impact on timing analysis error and design guardband • Traditional ‘unimodal’ analysis may not be viable for DPL • Our analysis: 20% or greater change in timing • Self-compensation strategies, along with BEOL biasing, can reduce impact of bimodal CD variation • Work at UCSD: “Design-Aware Process Adaptation” • Ongoing work: more accurate, efficient and practical solutions to ‘bimodal-awareness’ challenges in timing analysis and circuit optimization

  14. BACKUP

  15. rise fall Input 1 Input 0 Input 1 Input 0 rise fall Impact on Cell Delay and Power • Monte Carlo simulations : #10K • DPL1: (2n-1)-th gate is group1 and 2n-th gate is group2 • DPL2: 2n-th gate is group1 and (2n-1)-th gate is group2 • Unimodal: CD distribution covers CDgroup1 CDgroup2 • Unimodal representation is too pessimistic • Characteristics of DPL1 and DPL2 are very different! Unimodal Bimodal group1 Bimodal group2 2n 64 66 59 61 54 56 60 Best CD Worst CD

  16. Impact on Design Guardband • Comparison of required design guardband • Unimodal approximation: conservative but easy • Lead to over-design • But can use conventional flow • Bimodal-aware: realistic but complex method • New bimodal-aware timing analysis and new timing-driven design optimizations are required

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