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The first microprocessor

It could be pedagogical to study a small 4 bit nibble computer in order to understand how real numbers are stored and handled! Normaly 32 bit registers are used, but the principles from the nibble computer will remain the same. The first microprocessor.

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The first microprocessor

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  1. It could be pedagogical to study a small 4 bit nibble computer in order to understand how real numbers are stored and handled! Normaly 32 bit registers are used, but the principles from the nibble computer will remain the same. William Sandqvist william@kth.se

  2. The first microprocessor Intel 4004 1971 was a 4 bit (nibble) processor. The customer Busicom wanted a dedicated calculator chip, but the disobedient engineers created a general purpose processor. William Sandqvist william@kth.se

  3. 4.3Imagine a ”Nibble” computer • Computer registers are ”rings”. A four bit register can hold 24 = 16 numbers. Either 8 positive (+0…+7) and 8 negative (-1…-8) ”signed numbers”, or 16 (0…F) ”unsignednumbers”. If a result is bigger than 16, the register overflows. (In some processors indicated with a Carry-flag). William Sandqvist william@kth.se

  4. Real numbers in Nibble computer • Imagine a ”Nibble” fixed point format, Q3! • Imagine a ”Nibble” floating point format! William Sandqvist william@kth.se

  5. Q3 [b3b2b1b0] Fixed point format The Q-format is the same as the signed numbers but downscaled: -1 < Q3 < 1-b0 The step between numbers is the weight of b0 0.125 Fixed point number line! Fixed point circle! William Sandqvist william@kth.se

  6. Floating point (Nibble) Floating point format Sign b3 Significand 1.b0 1.02 = 1.0101.12 = 1.510 Exponent b2b1-1 (exess1) 200-1 = 0.5201-1 = 1210-1 = 2211-1 = 4 + 1.0  0.5 = +0.5+ 1.0  1 = +1+ 1.0  2 = +2+ 1.0  4 = +4 + 1.5  0.5 = +0.75+ 1.5  1 = +1.5+ 1.5  2 = +3+ 1.5  4 = +6 - 1.0  0.5 = -0.5- 1.0  1 = -1- 1.0  2 = -2- 1.0  4 = -4 - 1.5  0.5 = -0.75- 1.5  1 = -1.5- 1.5  2 = -3- 1.5  4 = -6 Floating point number line! William Sandqvist william@kth.se

  7. Quantisation error Maximum Quantisation Error MQE: Fixed point: (2-3)/2 = 2-4 = 0.125/2 = 0.0625 Float: (6-4)/2 = 1 William Sandqvist william@kth.se

  8. The number Zero In fixed point formats the number zero is represented as [0000] In floating point format, there is no representation for zero! We could use, 0000 as +0 and 1000 as –0, as in the IEEE standard format! Floating point circle! The IEEE 32 and 64 bit float standard William Sandqvist william@kth.se

  9. Hawe you forgotten how? Converting Real numbers to Binary William Sandqvist william@kth.se

  10. 4.4 Six bit float Significand 1.b2b1b01.0002 = 1.000101.0012 = 1.125101.0102 = 1.25101.0112 = 1.375101.1002 = 1.5101.1012 = 1.625101.1102 = 1.75101.1112 = 1.87510 Exponent b4b3-1 (exess1)00-1 = -1 200-1 = 0.501-1 = 0 201-1 = 110-1 = 1 210-1 = 211-1 = 2 211-1 = 4 • 0.2510 = 0.012 = 1.02  2-2 exponent -2 not representable • 0.812510 = 0.11012 = 1.10122-1 representable • -1,37510 = -1.0112 = -1.0112  20 representable • 4.2510 = 100.012 = 1.00012  22 significand 1.0001 not representable • 7.510 = 111.12 = 1.1112  22 representable William Sandqvist william@kth.se

  11. Float Addition Algorithm:1. Check for zeroes2. Align significands3. Add/Sub significands4. Normalize result a = 0011112 0 01 111  + 011.111b = 0100102 0 10 010  + 10 1.010 Align significands. 10 > 01 shift smaller number a to right to get same exponent:Significand 0.1111 exponent 10 Normalize result: 10.0011 exp 10 1.00011 exp 11Rounding: 1.00011 ~ 1.001 Add significands: Result: 0 11 001 a = 1.875 b = 2.5 a+b = 4.5 (4.375) William Sandqvist william@kth.se

  12. Float Multiplication Simpler than addition! Algorithm: 1. Check for zeroes2. Add exponents and subtract Bias3. Multiply significands4. Normalize Exponents: 01 10 Bias = 1exp = 01+10 -1 = 10 Multiply significands Normalize result: 10.010110 exp 10 1.0010110 exp 11 Rounding: 1.0010110 ~ 1.001 Result: 0 11 001 a = 1.875 b = 2.5 a*b = 4.5 (4.6875) William Sandqvist william@kth.se

  13. IEEE – 32 bit float By using the exess–127 format for the exponent, we can compare floats as if they were sign and magnitude integers! Dec  IEEE-754 William Sandqvist william@kth.se

  14. William Sandqvist william@kth.se

  15. 5-4 Cache conflict misses Data cache 1 k Word (Word = 32 bit). Cache line 4 Words. Conflict misses depending on memory placement of x and a? for (i = 0; i < 50; i++)for(j = 0; j < 4; j++) x[i][j] = a[i][j] * c[i]; William Sandqvist william@kth.se

  16. Memory – Cache adressmapping Memorys are often Byte-organized, but we could draw it as if it was organized in Memory-lines with the same size as the Cache-line. If the CPU needs a data-item in a line, the whole line is transfered fom memory to cache. Direct addressmapping: Memory-line: i Cache-line: j = i % K William Sandqvist william@kth.se

  17. a and x always conflict miss … for(j = 0; j < 4; j++) x[i][j] = a[i][j] * c[i]; Conflict miss if the distans between the startaddress in memory of a and of x is a multiple of 1 k Words, 4096 Bytes. William Sandqvist william@kth.se

  18. a and x conflict miss 1:4 … for(j = 0; j < 4; j++) x[i][j] = a[i][j] * c[i]; Conflict miss 1:4 if the distans between the startaddress in memory of a and of x is a multiple of 1 k Words  3 Words, 4096 Bytes  12 Bytes. William Sandqvist william@kth.se

  19. a and xno conflict miss … for(j = 0; j < 4; j++) x[i][j] = a[i][j] * c[i]; No conflict miss if the distans between the startaddresses in memory of a and of x is not a multiple of 1 k Words, and not a multiple of 1 k Words 3, 2, 1 Words! William Sandqvist william@kth.se

  20. William Sandqvist william@kth.se

  21. 8-1 Arbitration 3 Masters and 4 Slaves are connected to a classical bus. Read access pattern: Sequential execution, 7 cycles needed. 1. M1  Rd S12. M2  Rd S23. M3  Rd S44. M2  Rd S35. M3  Rd S36. M2  Rd S27. M1  Rd S1 Many other alternatives are possible! William Sandqvist william@kth.se

  22. Slave side arbitration Weighted round robin slave-side arbitration. Connections and weights: • Best case execution time (3 cycles) • M1  Rd S1 ; M2  Rd S2 ; M3  Rd S4 • M1  Rd S1 ; M2  Rd S3 ; • ; M2  Rd S2 ; M3  Rd S3 • Worst case execution time (4 cycles) • M1  Rd S1 ; M2  Rd S2 ; M3  Rd S4 • M1  Rd S1 ; ; M3  Rd S3 • ; M2  Rd S3 ; • ; M2  Rd S2 ; William Sandqvist william@kth.se

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