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Four-Bit Serial Adder. By Huong Ho, Long Nguyen, Lin-Kai Yang Ins: Dr. David Parent Date: May 17 th , 2004. Agenda. Abstract Introduction Project Details Summary of Results Conclusions. Abstract.

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four bit serial adder

Four-Bit Serial Adder

By Huong Ho, Long Nguyen, Lin-Kai Yang

Ins: Dr. David Parent

Date: May 17th, 2004

agenda
Agenda
  • Abstract
  • Introduction
  • Project Details
  • Summary of Results
  • Conclusions
abstract
Abstract

We designed an 4-bit serial adder that operated at 200 MHz and used of power 10.75mW and occupied an area of 192x60 um².

introduction
Introduction
  • Bit-serial structure is designed to process the input one bit at a time, generally using the results of the operations on the first bit to influence the processing of subsequent bits.
  • Because it passes all the bits through the same logic, bit-serial reduces a significant amount of required hardware. Typically, the bit-serial approach requires 1/nth of the hardware required for the equivalent n-bit parallel design.
  • Bit-serial structure reduces signal routing (1-bit signals instead of n-bit signals) and higher-speed operation (one adder and a register rather than an n-bit adder).
introduction cont
Introduction (cont.)
  • The price of this logic reduction is that the serial hardware takes n clock cycles to execute, while the equivalent parallel structure executes in one clock cycle.
  • Bit-serial architectures have been used successfully in many applications that are dealing with a bit stream such as signal processing, audio, video etc…. It was extremely popular in the 2-5u technology range.
longest path calculations
Longest Path Calculations

Note: All widths are in microns and capacitances in fF

4 bit serial adder layout
4-bit Serial Adder Layout

Area = 192 x 60 um²

power consumption
Power Consumption

P = 10.75 mW

acknowledgements
Acknowledgements
  • Thank you Dr. Parent for being so patient!!!
  • Thanks to Cadence Design Systems for the VLSI lab.
  • Thanks to our classmates who helped us in the lab.