1 / 14

4-BIT CARRY LOOK AHEAD ADDER

4-BIT CARRY LOOK AHEAD ADDER. Jaime Cordoba Advisor: Dave Parent May 19, 2004. Agenda. Abstract Introduction Why Simple Theory Back Ground information (Lit Review) Summary of Results Project (Experimental) Details Results Cost Analysis Conclusions. Abstract.

Samuel
Download Presentation

4-BIT CARRY LOOK AHEAD ADDER

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript


  1. 4-BIT CARRY LOOK AHEAD ADDER Jaime Cordoba Advisor: Dave Parent May 19, 2004

  2. Agenda • Abstract • Introduction • Why • Simple Theory • Back Ground information (Lit Review) • Summary of Results • Project (Experimental) Details • Results • Cost Analysis • Conclusions

  3. Abstract • I designed an 4-bit carry look ahead adder that operates at a frequency of 200 MHz and has a propagation delay of .5ns and occupies an area of 375 x 160mm^2

  4. Introduction • Carry look ahead adders are important because they are building blocks for other logics such as MSI adders and ALUs. • The carry look ahead logic is the adder stage that generates a carry and propagates carry

  5. Project Details • Hand Calculations • Cell based technique • Build each layout of gate seperately and performed an LVS • Final Schematic • Final Layout • Final Simulation

  6. Longest Path Calculations Note: All widths are in microns and capacitances in fF

  7. Schematic

  8. Layout

  9. Verification

  10. Simulations

  11. Cost Analysis • Time spent on each phase of project • verifying logic= 10 hours • verifying timing= 5 hours • Layout= 25 hours • post extracted timing= 5 hours

  12. Lessons Learned • Do not procrastinate • Start as early as possible • Make a schedule and follow it • Talk to your instructor

  13. Summary • My objective was to design a 4-bit carry look ahead adder with a propagation delay of .5ns • Carry adders are important and are implemented in ALUs and other logics

  14. Acknowledgements • Thanks to my wife for putting up with me • Thanks to Cadence Design Systems for the VLSI lab • Thanks to Synopsys for Software donation • A million thanks to Professor Dr. Parent

More Related