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CE00550-1 Computer & MultiMedia Hardware Systems

CE00550-1 Computer & MultiMedia Hardware Systems. Memory Systems By Ian Sunley. Introduction. We showed last lecture how a Flip Flop can act as memory. This lecture will examine why we need memory and what other forms of memory are available. Types of Memory. ROM – Read Only memory

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CE00550-1 Computer & MultiMedia Hardware Systems

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  1. CE00550-1 Computer & MultiMedia Hardware Systems Memory Systems By Ian Sunley

  2. Introduction • We showed last lecture how a Flip Flop can act as memory. • This lecture will examine why we need memory and what other forms of memory are available.

  3. Types of Memory • ROM – Read Only memory • RAM – Random Access memory • FLASH – Erasable RAM

  4. Memory • Introduction • An ability to store one or more bits of information. • E.g. A D type latch can store one bit of information. • D type latch uses many transistors to store one bit. (Takes up too much space) • Need a more efficient way to store bits. • D type latch looses information when power is removed

  5. Memory • Need to organise the storage in bytes • Need to store many bytes in one chip • Cannot have a separate line(pin) to access each byte • Hence we need addressing (3 lines can access up to 8 bytes) • Must be able to read the data out • May wish to write new data in

  6. Memory • Block Diagram (read) Read A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 8 bytes storage Value on address lines determines which byte is outputted

  7. Memory • Block Diagram (write) write A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 8 bytes storage Value on address lines determines which byte data is written into

  8. Read Only Memory ROM • Data is permanently stored in the device • stored during the construction of the device, by the physical location of transistors • remains stored when power removed • cannot be altered • Devices can be mass produced all with the same data • high volume low cost

  9. Read Only Memory ROM • Used to store Operating Systems in older computers • BBC, Spectrum, Archimedes, Commodore • but upgrading the OS meant replacing the ROM chips • Now only used for some earlier BIOS chips and controller cards

  10. +5v +5v +5v +5v Read Only Memory ROM D3 D2 D1 D0 2 to 4 bit decoder A1 A0

  11. +5v +5v +5v +5v Read Only Memory ROM 1 1 1 1 = 0 = 0 = 0 = 0 D3 D2 D1 D0 A1 A0

  12. +5v +5v +5v +5v Read Only Memory ROM D3 D2 D1 D0 A1 A0 0 0

  13. +5v +5v +5v +5v Read Only Memory ROM 00 D3 D2 D1 D0 1 0 0 0 0 0 A1 A0

  14. +5v +5v +5v +5v Read Only Memory ROM 00 0 0 1 1 = 1 = 1 = 0 = 0 D3 D2 D1 D0 1 0 0 0 0 0 A1 A0

  15. +5v +5v +5v +5v Read Only Memory ROM 00 01 10 11 1 1 1 0 = 0 = 0 = 0 = 1 D3 D2 D1 D0 0 0 0 1 1 1 A1 A0

  16. Random Access Memory RAM • Random ? • Different to First in First Out (FIFO) • Different to First In Last Out (FILO) • Any block of memory can be accessed in any order at any time • Read /Write memory • We can write data to it • We can read data from it

  17. Static RAM • A bits is stored in a flip-flop arrangement of two transistors (similar to D type flip-flop) • Array of flip-flops allow storage of many blocks of groups of bits • Associated gates are required to allow read and write access • Fast to access ~ 5 - 10 ns • But takes up a lot of space per bit (cannot pack loads onto a chip

  18. Dynamic RAM • Bits are stored in a capacitor with one transistor to provide access • Capacitor requires refreshing regularly to stop data leaking away • Associated gates are required to allow read and write access • Slow to access ~70 ns • But takes up very little space per bit (can pack loads onto a chip)

  19. Programmable ROM (PROM) • ROM’s are programmed in the manufacturing process • costly to produce unless very high volume • prototyping during development ? • small runs (a few thousand) ? • Need to be able to program ROM’s locally • Hence the PROM

  20. Programmable ROM (PROM) • Manufacture like a ROM, but with a transistor at each cross-point • Fuseable link connects transistor to select line • Programming the PROM uses a high voltage (27 v) to blow the links not required • Once ‘blown’, the PROM cannot be re-programmed

  21. Erasable PROM (EPROM) • During development programmed PROMS are discarded. • Would be good if data could be erased • Use a FAMOS (Floating Gate Metal Oxide Semiconductor Transistor)

  22. Erasable PROM (EPROM) • Like a ROM with a transistor at each cross point • Charge can be trapped in small regions within each transistor by programming with a high voltage • Charge can only be released by exposure to Ultraviolet light for 15 - 20mins • Small window in chip to allow light in

  23. Erasable PROM (EPROM) • Used during development work to save costs • Used in very small production runs

  24. Electrically Erasable PROM (E2PROM) • Enable PROM’s to be reprogrammed without any specialist equipment whilst still in situ. • Becoming like RAM ? • Very slow to program compared to RAM • Used in BIOS in PC’s so than BIOSs can be updated

  25. Memory mapping • Some memory chips are 8k • 0 - 8191 • 0 - 1FFF • 0 0000 0000 0000 - 1 1111 1111 1111 • (13 bits) • A12 to A 0 • We need 8 8K chips to make up 64 k of addressable memory for the processor.

  26. Memory mapping • How do we arrange 8 8k chips so that they appear as a continuous 64k of memory to the processor ? • Answer • Memory mapping

  27. 8k RAM RAM RAM RAM RAM RAM RAM RAM A12 A0 A12 A0 A12 A0 A12 A0 A12 A0 A12 A0 A12 A0 A12 A0 Address Bus Address Bus Address Bus Address Bus Address Bus Address Bus Address Bus Address Bus Memory mapping 8 A15 A0 ? Address Bus Processor

  28. EN 8k RAM A12 A0 EN 8k RAM A12 A0 EN 8k RAM A12 A0 EN EN EN EN 8k RAM 8k RAM 8k RAM 8k RAM EN A12 A0 A12 A0 A12 A0 A12 A0 8k RAM A12 A0 Memory mapping A15 A14 A13 A12 A0 Processor

  29. EN 3 to 8 Decoder 8k RAM A12 A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EN 8k RAM A12 A0 EN 8k RAM A12 A0 EN EN EN EN 8k RAM 8k RAM 8k RAM 8k RAM EN A12 A0 A12 A0 A12 A0 A12 A0 8k RAM A12 A0 Memory mapping A15 A14 A13 A12 A0 Processor

  30. EN 3 to 8 Decoder 8k RAM A12 A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EN 8k RAM A12 A0 EN 8k RAM A12 A0 EN EN EN EN 8k RAM 8k RAM 8k RAM 8k RAM EN A12 A0 A12 A0 A12 A0 A12 A0 8k RAM A12 A0 Memory mapping 0 0 0 A15 A14 A13 A12 A0 Processor Address 0 to 1FFF

  31. EN 8k RAM A12 A0 EN 8k RAM A12 A0 EN 8k RAM A12 A0 EN 8k RAM A12 A0 Memory mapping EN 3 to 8 Decoder 8k RAM 0 0 0 A12 A0 A15 A14 A13 A12 A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EN 8k RAM A12 A0 Processor EN 8k RAM A12 A0 EN 8k RAM A12 A0 Address 0 to 1FFF

  32. Memory mapping EN EN 3 to 8 Decoder 8k RAM 8k RAM 0 0 1 A12 A0 A12 A0 A15 A14 A13 A12 A0 Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0 EN EN 8k RAM 8k RAM A12 A0 A12 A0 Processor EN EN 8k RAM 8k RAM A12 A0 A12 A0 EN EN 8k RAM 8k RAM A12 A0 A12 A0 Address 2000 to 3FFF

  33. Summary • We now can see how a computer remembers data and also how we can store large amounts of data and address it. • Next Lecture we will have a look at the CPU itself and how it gets its data.

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