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Overview on CBM DAQ Boards Development

Overview on CBM DAQ Boards Development. Walter F.J. Müller , GSI, Darmstadt for the CBM Collaboration Workshop on Silicon Detector Systems for the CBM Experiment at FAIR GSI, 18-20 April 2007. n-XYTER – seen from the DAQ side.

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Overview on CBM DAQ Boards Development

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  1. Overview on CBM DAQ Boards Development Walter F.J. Müller, GSI, Darmstadt for the CBM Collaboration Workshop on Silicon Detector Systemsfor the CBM Experiment at FAIRGSI, 18-20 April 2007

  2. n-XYTER – seen from the DAQ side • The N-XYTER is quickly becoming the designated read-out solution for many CBM detector system prototypes: • obvious cases: • STS - Silicon strip detectors • MUCH/TRD – GEM chambers • plausible cases: • MUCH Silicon Pad chambers • RICH PMT • potential cases: • MUCH/TRD - MWPC chambers • The CBM-XYTER development just started. For several years to come the N-XYTER is thus the designated work horse for CBM detector prototyping. • We need a N-XYTER read-out chain to support • simple lab desk-top setups • medium-size test beam configurations with multiple sub-systems. Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  3. timewalkcomp. digitalFIFO tokencell peakdetect& hold analogFIFO timestampcounter tokenmanager outputdrivers n-XYTER Architecture PreAmp fast shaper comparator slow shaper 32 MHzreadoutrate 32 MHzreadoutrate peaking time fast: 20 ns slow: 140 ns 1 ns step outputs:1 analogdifferential 8 digital LVDS (4*32 MHz) Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  4. Basic n-XYTER Readout Chain Front-EndBoard Detector Read-OutController Active BufferBoard FEB ROC ABB Tag data XYTER Tag data XYTER MGT MGT ADC data FPGA ADC FPGA Tag data XYTER SFP SFP MGT MGT Tag data XYTER control clock Bond orcableconnection up to 8 N-XYTER1024 ch. LVDSsignalcable 2.5 Gbpsopticallink 1-4 lanePCIeinterface Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  5. Basic n-XYTER Readout Chain – cont. Front-EndBoard Detector Read-OutController Active BufferBoard FEB ROC ABB Tag data XYTER Tag data XYTER MGT MGT ADC data FPGA ADC FPGA Tag data XYTER SFP SFP MGT MGT Tag data XYTER control clock likelydifferentform factorsneeded one ROCfor all SiliconorGEM dets keep thisinterfacecommon Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  6. Scalable n-XYTER Readout Chain Front-EndBoard Detector Read-OutController Data CombinerBoard FEB ROC DCB Tag data XYTER Tag data XYTER MGT SFP SFP MGT MGT ADC data FPGA ADC FPGA Tag data XYTER SFP MGT Tag data SFP MGT XYTER control clock data andtime syncover sameserial link to otherROC's to ABB Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  7. Some Configurations Minimal Configuration PC Detector FEB ROC ABB Expandable Configuration Detector FEB ROC Detector FEB ROC PC DCB ABB Detector FEB ROC Detector FEB ROC Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  8. ROC → SysCore based to FEB to ABBorDCB Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  9. Basic Components and Interfaces • Xilinx Virtex4 FPGA • 320 up to 576 user I/Os • LAN interfaces • SD-Card connector • LAN, USB, JTAG • programming capability • via CPLD • RS232 interface • High Speed Serial Ports (MGTs) • DDR SDRAM • user definable I/O • Watchdog slide courtesy D. Gottschalk

  10. SysCore Features (Remote) Configuration: via standard JTAG or select map configuration via USB to JTAG bridge via LAN Watchdog triggered Radiation tolerant by fast configuration/reboot Linux on FPGA Fast Boot All features together in one design memory image plus processor state after boot is stored and reloaded. slide courtesy D. Gottschalk

  11. FPGA SEFI Mitigation • Most common FPGA's store the configuration in an internal SRAM • A SEU (single event upset) of a config SRAM cell can thus lead toa change on the functional behavior of the FPGA, called a SEFI (single event functional interrupt). • Upset rates are of the order of 1 SEFI per 108 p/cm2 • Note: • most config SRAM bits are not used (a single SEU doesn't matter) • multiple flipped unused config SRAM bits can lead to functional errors • Thus strategy: • scrubbing – rewrite config SRAM periodically • Xilinx Virtex-2, -4, and -5 devices allow glitch-free config update •  refresh config memory periodically during normal operation FPGAVirtex-4 ControllerActel ProAsic3 FlashMemory watch dog Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  12. Enhanced FPGA refresh technology for radiation tolerance • Mode 1: Initial configuration • Mode 2: Refresh of the configuration memory (SRAM) • either: continuously overwriting with the correct configuration • or: overwriting on demand (after error detection) • Mode 3: Error detection: • Read back of the configuration memory • Checking (compare or checksum) • Virtex 4: internal Hamming functionality • Mode 4: Watchdog triggers start of the failsafe configuration if design fails. as was developed for the Alice RCU board slide courtesy D. Gottschalk

  13. DCB → use 'HTX-Board' any board with manySPF's on V-4 MGT'swill do, e.g. ALICE GTU six V-4 MGT based optical links Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  14. ABB → V1 ready soon V-4 MGT basedoptical link V-4 MGT basedPCIe interface(4 lanes) Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  15. The End Thanks for your attention We acknowledge the support of the European Community-Research Infrastructure Activity under the FP6 "Structuring the European Research Area" programme (HadronPhysics, contract number RII3-CT-2004-506078). Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  16. The End Thanks for your attention Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  17. digitalFIFO digitalFIFO tokencell tokencell analogFIFO analogFIFO Token Ring Readout Token Cell Processes: on token, check for data, either initiate readout in clockcycle or pass forward token • Token asynchronously passes from channel to channel in search of data • Within one clock cycle token could pass through all channels • use 2 stage logic design to keep logic path short and allow scan of 128 channels in one clock cycle • If token encounters occupied channel, data readout is initiated (1 clock cycle) • After readout of one hit the token passes to the next occupied channel. • Token manager ensures that there is one and only one token is circling • Readout clock: 32 MHz tokenmanager outputdrivers Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

  18. . . . DACsslowcontrol I2Cinterface Putting it together: n-XYTER ASIC 128 channels timestampcounter tokenmanager outputdrivers Note: there is also a 32 channel version for MSGC readout called MSGCROC outputs:1 analogdifferential 8 digital LVDS (4*32 MHz) Workshop on Silicon Detector Systems for the CBM Experiment at FAIR -- Walter F.J. Müller, GSI

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