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3. Digital Implementation of Mo/Demodulators. DSB. MOD. amp. SSB. DEM. amp. General Structure of a Mo/Demodulator. Single Side Band (SSB) Modulator. MOD. SSB. Implementation using Real Components. SSB. where. Single Side Band (SSB) Demodulator. DEM. LPF.

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Presentation Transcript
slide2

DSB

MOD

amp

SSB

DEM

amp

General Structure of a Mo/Demodulator

slide6

Single Side Band (SSB) Modulator in Discrete Time

Modulator Implemented in two stages:

Digital Up Converter

DUC

Analog MOD

ZOH

DISCRETE TIME

CONTINUOUS TIME

slide7

Single Side Band (SSB) Demodulator in Discrete Time

Demodulator Implemented in two stages:

Digital Down Converter

DDC

Analog DEM

ZOH

CONTINUOUS TIME

DISCRETE TIME

slide8

Digital Down (DDC) and UP (DUC) Converters

DUC

DDC

RF

Baseband

  • MHz for voice
  • GHz for data
  • kHz for voice
  • MHz for data

Order of magnitude of resampling:

slide9

LPF

LPF

Problem with Large Upsampling Factor

if M is large, very small transition region

high complexity filter

slide10

Problem with Large Downsampling Factor

LPF

LPF

if M is large, very small transition region

high complexity filter

slide11

Solution: Upsample in Stages

In order to make it more efficient we upsample in L stages

slide13

Example: Upsample in One Stage

This is not only a filter with high complexity, but also it is computed at a high sampling rate.

slide14

Same Example in Three Stages

Total Number of operations/sec=

a 95% savings!!!!

slide16

i-th Stage of Downsampling

noise

keep aliased noise away from signal

slide18

Same Example in Three Stages

Total Number of operations/sec =

… a savings of almost 99% !!!

slide19

Stages at the Highest Rates

highest rates

  • the highest sampling rates are close to carrier frequencies, thus very high;
  • properly choose intermediate frequencies to have simple filters at highest rates
slide22

Very simple Low Pass Filter: the Comb Integrator Cascade (CIC)

same!!!

“Comb”

“Integrator”

these two are the same!

Notice: no multiplications!

slide24

Impulse Response of the CIC

interpolating sequence

slide25

The CIC in the Time Domain

like a discrete time ZOH!

slide26

Two Important Identities: The “Noble” Identities

Same !!!

As a consequence we have one of two “Noble Identities”:

Same!!!

slide27

Other “Noble” Identity

Same !!!

As a consequence we have the other of the two “Noble Identities”:

slide28

Efficient Implementation of Upsampling CIC

Use Noble Identity:

Very simple implementation (no multiplications):

slide29

Efficient Implementation of Downsampling CIC

Use Noble Identity:

Very simple implementation (no multiplications):

slide30

Frequency Response of the CIC

5

0

-5

only 13 dB attenuation

dB

-10

-15

-20

-25

0

0.1

0.2

0.3

0.4

0.5

f=F/Fs

Not a very good Low Pass Filter. We want a better attenuation in the stopband!

slide31

Put M Stages together

Frequency Response:

slide32

Improved Frequency Response of CIC Filter

Resampling Factor N=10

With M=4 or 5 we already get a very good attenuation.

slide36

Problem: DownSampling CIC is Unstable

Now we have to be careful: the output of the integrator will easily go to infinity

slide37

CIC Implementation.

At the p stage:

This implies:

and

slide38

If we use Q bits for the integrators then we need to guarantee

Let the input data use L bits:

Then:

decimation factor

input bits

number of stages

slide39

Application: Software Defined Radio

  • Definitions:
  • Software Defined Radio: modulation, bandwidth allocation … all in software
  • Field Programmable Gate Array (FPGA): reprogrammable logic device which is able to perform a number of operations in parallel. They can process data at a rate of several 100s of MHz
  • DSP Chip: optimized for DSP operations by some hardwired ops (such as multiplies).
slide40

An HF SSB Software Defined Radio

by Dick Benson, The Mathworks,

64MHz

15.6kHz

7.8kHz

RF

IQ

AUDIO

Rec.

Rec.

Rec/Tr

Trans.

Trans.

DAC

IQ

AUDIO

RF

FPGA

DSP Chip

slide41

Transmitter:

AUDIO

I

FIR

SSB

FIR

Q

DSP Chip

Xilinx Library Modules

I

FIR

FIR

CIC

RF

Q

FIR

FIR

CIC

FPGA

slide42

Receiver:

Xilinx Library Modules

I

RF

CIC

FIR

FIR

Q

CIC

FIR

FIR

FPGA

I

FIR

AUDIO

Q

FIR

DSP Chip