The Development of Psec-Resolution TDC for Large Area TOF Systems. Fukun Tang Enrico Fermi Institute University of Chicago. With Karen Byrum and Gary Drake (ANL) Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David Yu (UC). From H. Frisch.
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Enrico Fermi Institute
University of Chicago
With Karen Byrum and Gary Drake (ANL)
Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David Yu (UC)
From H. Frisch Systems
Output at anode from simulation of 10 particles going through fused quartz window- T. Credo, R. Schroll
Ability to simulate electronics and systems
to predict design performance
Jitter on leading edge 0.86 psec
MCP_PMT Output Signal
1 ps Resolution Time-to-Digital Converter!!!
2 Ghz PLL
psFront-end (Timing Module Option #1)
Electronics with typical gate jitters << 1 psec
(2) Time Stretcher
2 Ghz PLL
psFront-end (Timing Module Option #2)
x200 StretchedTime Interval (Output Signal )
Stretched Time = 274ns
1ns Time Interval (Input Signal)
0 50ns 100ns 150ns 200ns 250ns 300ns
PD: Phase Detector
CP: Charge Pump
LF: Loop Filter
VCO: Voltage Controlled Oscillator
Negative Resistance and Current-Limited Voltage Control Oscillator with Accumulating PMOS Varicap and 50W Line Drivers
VControl varied 0.18V
[email protected] loads
Phase Noise @100KHZ offset
(1) VCO time-jitter met our requirement.
(2) Post layout simulation matched schematic simulation very well.
(3) Some problems we have encountered with pcell library, layout, DRC, LVS and auto-routing functionalities.
(4)Ready for October Submission.