The development of psec resolution tdc for large area tof systems
Download
1 / 25

The Development of Psec-Resolution TDC for Large Area TOF Systems - PowerPoint PPT Presentation


  • 310 Views
  • Uploaded on

The Development of Psec-Resolution TDC for Large Area TOF Systems. Fukun Tang Enrico Fermi Institute University of Chicago. With Karen Byrum and Gary Drake (ANL) Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David Yu (UC). From H. Frisch.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'The Development of Psec-Resolution TDC for Large Area TOF Systems' - sherlock_clovis


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
The development of psec resolution tdc for large area tof systems l.jpg

The Development of Psec-Resolution TDC for Large Area TOF Systems

Fukun Tang

Enrico Fermi Institute

University of Chicago

With Karen Byrum and Gary Drake (ANL)

Shreyas Baht, Tim Credo, Henry Frisch, Harold Sanders and David Yu (UC)


Major advances for tof measurements l.jpg

From H. Frisch Systems

Output at anode from simulation of 10 particles going through fused quartz window- T. Credo, R. Schroll

Major advances for TOF measurements:

Ability to simulate electronics and systems

to predict design performance

Jitter on leading edge 0.86 psec


Requirement psec resolution tdc l.jpg
Requirement: Psec-Resolution TDC Systems

MCP_PMT Output Signal

Start

500pS

Reference Clock

Stop

Tw

1 ps Resolution Time-to-Digital Converter!!!


Diagram of mcp pmt electronics from harold l.jpg
Diagram of MCP-PMT Electronics SystemsFrom Harold


Approaches possibilities l.jpg
Approaches & Possibilities Systems

(1) TAC-ADC

1/4

“Zero”-walk Disc.

TAC

Driver

11-bit ADC

Receiver

PMT

2 Ghz PLL

REF_CLK

4x1Ghz PLL

psFront-end (Timing Module Option #1)


Tac adc simulation result l.jpg

TAC-ADC: Systems Simulation Result

Electronics with typical gate jitters << 1 psec


Approaches possibilities7 l.jpg
Approaches & Possibilities Systems

(2) Time Stretcher

1/4

“Zero”-walk Disc.

Stretcher

Driver

11-bit Counter

Receiver

PMT

CK5Ghz

2 Ghz PLL

REF_CLK

psFront-end (Timing Module Option #2)


Time stretcher simulation result l.jpg
Time Stretcher: SystemsSimulation Result

x200 StretchedTime Interval (Output Signal )

Stretched Time = 274ns

(pedestal=74ns)

1ns Time Interval (Input Signal)

0 50ns 100ns 150ns 200ns 250ns 300ns


Vco submission of oct 2006 l.jpg
VCO: Submission of Oct. 2006 Systems

Ultimate Goal:

  • To build TDC with 1 pSec Resolution for Large Scale of Time-of-Flight Detector.

    Primary Goal:

  • To build 2-Ghz VCO, key module of PLL that generates the TDC reference signal

    • Cycle-to-Cycle Time-jitter < 1 ps

  • To evaluate IHP SG25H1/M4M5 Technology for our applications

  • To gain experiences on using Cadence tools (Virtuoso Analog Environment)

    • Circuit Design(VSE)

    • Simulation(Spectre)

    • Chip Layout(VLE, XLE, VCAR)

    • DRC and LVS Check (Diva, Assura, Calibre)

    • Parasitic Extraction(Diva)

    • Post Layout Simulation(Spectre)

    • GDSIIStream out

    • Validation

    • Tape Out


  • Diagram of phase locked loop l.jpg
    Diagram of Phase-Locked Loop Systems

    CP

    Fref

    I1

    Uc

    PD

    VCO

    F0

    LF

    I2

    1N

    PD: Phase Detector

    CP: Charge Pump

    LF: Loop Filter

    VCO: Voltage Controlled Oscillator


    Ihp sg25h1 0 25 m m sige bicmos technology l.jpg
    IHP (SG25H1) 0.25 Systemsmm SiGe BiCMOS Technology

    • 0.25mm BiCMOS technology

    • 200Ghz NPN HBT (hetero-junction bipolar transistor)

    • MIM Capacitors (layer2-layer3) ( 1f/1u2 )

    • Inductors (layer3-layer4)

    • High dielectric stack for RF passive component

    • 5 metal layers (Al)

    • Digital Library: Developing



    2 ghz bicmos vco schematic l.jpg
    2-GHz BiCMOS VCO Schematic Systems

    Negative Resistance and Current-Limited Voltage Control Oscillator with Accumulating PMOS Varicap and 50W Line Drivers


    V f plot 3 model cases @ 27c 55c l.jpg
    V-F Plot (3 model cases @ 27C-55C) Systems

    Frequency

    Temperature:27C-55C

    Supply:VDD=2.5V

    VControl varied 0.18V

    VControl


    Phase noise 3 model cases @ 27c l.jpg
    Phase Noise ( 3 model cases @ 27C) Systems

    @100KHz offset

    Worst

    Typical

    Best

    Temperature:27C

    Supply:VDD=2.5V



    2 ghz vco performance summary 1 l.jpg
    2-GHz VCO Performance Summary Systems (1)

    T=27C

    f0 = 2 GHz phase noise: [email protected] offset


    2 ghz vco performance summary 2 l.jpg
    2-GHz VCO Performance Summary (2) Systems

    T=55C

    f0 = 2 GHz phase noise: [email protected] offset




    Diagram of post layout simulation l.jpg
    Diagram of Post Layout Simulation Systems

    Schematic

    Analog_extracted


    Transit analysis comparison of schematic and post layout simulations l.jpg
    Transit Analysis: Comparison of Schematic and Post Layout Simulations

    [email protected] loads

    Schematic

    Post Layout


    V f plot comparison of schematic and post layout simulations l.jpg
    V-F Plot: Comparison of Schematic and Post Layout Simulations

    Frequency

    PostLayout

    Schematic

    Vcontrol


    Phase noise post layout simulations vdd 2 5v temp 27c 55c l.jpg
    Phase Noise: Post Layout Simulations SimulationsVDD=2.5V Temp.=27C, 55C

    Phase Noise @100KHZ offset


    Conclusion l.jpg
    Conclusion Simulations

    (1) VCO time-jitter met our requirement.

    (2) Post layout simulation matched schematic simulation very well.

    (3) Some problems we have encountered with pcell library, layout, DRC, LVS and auto-routing functionalities.

    (4)Ready for October Submission.


    ad