Status of Sensor Irradiation and Bump Bonding

1. Status of Sensor Irradiation and Bump Bonding P. Riedler, G. Stefanini P. Dalpiaz, M. Fiorini, F. Petrucci

2. Outlook • Status of sensor irradiation • Next steps • Status of processed IRST wafers • Short overview of process steps in bump bonding • Thinning options to reduce material budget - possible problems

3. First Irradiated Samples • 6 Diodes from 2 IRST sensor wafers (200µm) • Diced at IRST • PCBs provided by M. Glaser • Transport boxes built by A. Gonidec • Diodes mounted and bonded by I. Macgill

4. T B Slide by C. Piemonte, A. Pozza, M. Boscardin/IRST

5. Diodes • Diodes A (7 mm x 7 mm, multi-guard) • Diodes B (3 mm x 3 mm, multi-guard) A1: wafer 570-T A2: wafer 566-B B1: wafer 570-T, 4 multi B2: wafer 570-T, 12 multi B3: wafer 566-B, 4 multi B4: wafer 566-B, 12 multi

6. Pre-Irradiation Tests • I-V and C-V measured in RD50 lab at CERN • Total leakage current at 23.7°C • C-V indicate Vfd~15V • One diode (B1) with higher current (~4µA)

7. Irradiaton in Ljubljana • TRIGA reactor, 250kW, irradiation with fast neutrons • Samples are irradiated in a tube placed in the reactor core occupying the position of one rod • Samples transported by M. Glaser, irradiation done by I. Mandic/JSI Ljubljana - end December 2005

8. Irradiation in Ljubljana • All diodes biased at 30V during irradiation • Guard and pad contact connected together • Immediately after irradiation stored in freezer (-20°C) • Irraditiation to different fluences: 2E14 1MeV n/cm2: A1, B1 3E13 1MeV n/cm2: A2 1E13 1MeV n/cm2: B4 2E12 1MeV n/cm2: B3 1E12 1MeV n/cm2: B2

9. Fluences in the GGT A1,B1 • Fluences: 1 MeV n equivalent cm2 • Added safety factor of 2 A2 B4 B3 B2

10. Annealing • Diodes were returned to CERN beginning of February • Measurements to be carried out using CERN setup • Apart from 8 hour car transport, diodes were stored at -20°C at all time after irradiation to slow down annealing • Annealing study according to ROSE standards with I-V and C-V measurements planned in the next weeks • Operating temperature assumed to be approx. 5°C (to be discussed)

11. Further Irradiations • More irradiations can be carried out using the T7 facility at CERN • Alternatives: Ljubljana, Helsinki • Few diodes still available from two diced wafers • More diodes will become available from processed wafers in short time

12. Bump Bonding and Thinning

13. Status of IRST Wafers at VTT • Wafers 565 and 571 sent to VTT for processing (autumn 2005) • Both wafers showed strong bow (~60-70µm) - potential problem for bb processing (max. 30 µm) • Visual inspection showed excellent quality • Both IRST wafers were broken in the photo-resist track at VTT • Probably the bow of the wafers and tight limits in the centering stage caused the breaking of the wafers. • The limit settings have been changed and tested with blank 4” wafers • New reworked wafers with smaller bow already arrived at VTT and will be processed this week

14. Status of IRST Wafers at VTT • In week 8 a fire occurred in the VTT cleanroom which affected some processing steps • For sensor wafers i.e. the electroplating step (Ni and Pb-Sn deposition) and the reflow oven were affected • Equipment needed to be moved to second cleanroom, cleaned and inspected • No wafer processing possible until this week

15. Process Steps for Flip Chip in M1 Sputtering of Ti-W/Cu Field Metal Photolithography M1 Electroplating (Ni/Pb-Sn) Field Metal Etching M1 = 'Old' Side of Clean Room M1 Post-plating Reflow (Optional) Back Grinding Only r.o. wafers M1 (Optional) CMP Polishing Dicing Flip Chip (Tack) Bonding M1 Assembly Reflow J. Salonen/VTT

16. Thinning • Goal: thin readout chips to 100µm or less to reduce material budget (no margin for sensor wafers due to signal!) • First thinning tests carried out before VTT fire • One blank 200µm wafer thinned successfully to 100µm • Next tests (as soon as CMP is back up): thin bumped 200µm wafer to 100µm and dice • Discussion with VTT end of March concerning thinning - several points of concern were discussed and tests planned

17. Considerations Concerning Thinning • Two options: bump deposition before thinning (ALICE) or after thinning • Problem: wafers after thinning are very fragile - might not survive bumping process unless a support wafer is attached to it (wafer bonding) • If bumping is done before thinning one critical step remains: removal of the protection tape used during grinding

18. Considerations Concerning Thinning • Tests are necessary to test which process order is best • Wafer bonding experience exists at VTT • New lamination tape being investigated • Further consideration: stress on thin wafers

19. Considerations Concerning Thinning • Back side grinding induces damage layer in the crystal -> stress • CMP helps to remove part of this damage layer • Trials necessary to optimize thinning with respect to stress on wafer (depends also on front side process) • Additional suggestion: deposition of compensation layer on thinned wafer back side

20. Considerations Concerning Thinning • Stress is also induced due to dicing of the thinned wafer (cutting of individual chips) • First observations already with ALICE chips 150µm chip

21. Considerations Concerning Thinning • Possible steps to reduce stress on chip edges: • Investigate dicing parameters • Backside layer deposition could present improvement • Laser cutting instead of diamond blade dicing • Tests required

22. Conclusion • First diodes irradiated in Lubljana • Annealing studies to be carried out in next weeks • First 200 mm blank wafer thinned to 100µm • Detailed studies required to optimize processing steps for thin wafers and to reduce stress • Processing of the reworked sensor wafers and thinning tests will continue as soon as possible