IEE5011 –Fall 2013 Memory Systems Wide I/O High Bandwidth DRAM

1. IEE5011 –Fall 2013Memory SystemsWide I/O High Bandwidth DRAM Yi-Lin, Tu Department of Electronics Engineering National Chiao Tung University b22531423@hotmail.com

2. Outline Introduction Proximity Communication A Wide I/O DRAM Architecture Conclusion Reference

3. Introduction • Memory gap • How to solve this problem? • Other techniques?

4. Proximity Communication A wireless chip-to-chip communicationtechnology. Two chips are placed face to face and their bonding pads are allowed to come within close proximity of each other without touching.

5. Proximity Communication

6. Proximity Communication • Advantages • Increase I/O density • Remove the on/off chip wires • Remove the on-die termination • Ease of testability • Remove the ESD structures

7. Proximity Communication • Parallel plate capacitance • 、 、 • Channel • 50 fF • 200 signals/ • 20 times greater than normal DRAM

8. Proximity Communication • Challenges • Mechanical misalignment • Supplying power to chips • Thermal removal

9. Proximity Communication • Mechanical misalignment • Six axis • Multiple source

10. Proximity Communication • Electronic sensor • Chip to chip separation sensor • Vernier scale(translation)

11. Proximity Communication • Electronic re-alignment • Use receiver and transmitter array. • This array has the ability to electrically reposition the transmitter pads to align the transmitter and receiver pads.

12. A Wide I/O DRAM Architecture • Using 4Gb DRAM as the starting point for developing a wide I/O DRAM architecture.

13. A Wide I/O DRAM Architecture • Pad moving • Moving the I/O channel to the edge. • Data and comment signals will need to be buffered at the center. • Allows the local column circuitry to be moved to the center.

14. A Wide I/O DRAM Architecture • Centralizing • Limit the bandwidth of the column and row path. • It’s possible by using proximity communication. • Increase the array efficiency.

15. A Wide I/O DRAM Architecture • Conventional DRAM chips operate with eight internal memory bank. • Enable eight wordlines to be active at once, one of each bank. • Possible to perform sequential column access to each bank. • Remove the large row access latency.

16. A Wide I/O DRAM Architecture • 512Mb bank structure • 4 possible arrangements for creating a 512Mb memory bank. • Keep the global I/O metal lines short allows for a higher bandwidth on an open page. • C and D are preferred.

17. A Wide I/O DRAM Architecture

18. A Wide I/O DRAM Architecture • Challenges • Number of metal layers • Global I/O routing • Local I/O routing

19. A Wide I/O DRAM Architecture • Number of metal layers and global I/O routing • A wide I/O architecture with 64 data pins operating with burst length of eight, and therefore a pre-fetch of 8n, requires 512 bits to be accessed in parallel. • The highest level of metal is used for global I/O routing and metal one is for global wordlines. • Increase the parasitic of each wordline.

20. A Wide I/O DRAM Architecture • Divide the 8k page • 256 bits per half-bank • This enables a possibility of increasing the number of global I/O tracks from 512 to 1024 or higher.

21. A Wide I/O DRAM Architecture • Local I/O routing • The large number of global I/O tracks requires 32 data signals from each 256 kb memory array. • Moving 32 data signals from the bitline sense amplifiers to the global I/O track is a major challenge due to the limited routing space above the bitline sense amplifiers. • Signals can be routed to the top and bottom of each 256kb memory segment.

22. A Wide I/O DRAM Architecture • Summary • Developing a wide I/O DRAM architecture that is suitable for Proximity Communication requires the communication channel to be moved to the side of the DRAM chip. • A distributed page and bank structure was developed to enable the possibility of using Proximity Communication with 32 data pins. • Reaching the use of 64 data pins required architectural changes that would not increase the manufacturing cost compared to current DRAM architectures.

23. Conclusion A DRAM architecture that uses proximity communication to increase the off-chip bandwidth while scaling the number of data pins. Proximity communication allows for an increase of I/O density, ease of testability, removal of ESD structures and resistive termination. Electrical sensors and electrical re-alignment techniques has enabled proximity communication to become a viable I/O technology. The challenges of creating a wide I/O architecture were found to be in the global and local I/O routing.

24. Reference Q. Harvard, “Wide I/O DRAM architecture utilizing proximity communication,” Master’s thesis, Boise State University, December 2009. Q. Harvard, R. J. Baker, and R. Drost, “Main memory with proximity communication: A wide I/O DRAM architecture,” in Proc. IEEE Workshop Microelectron.Electron Devices, Apr. 2010, pp. 1–4. Harvard, Q., Baker, R.J., “A scalable I/O architecture for wide I/O DRAM,” 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 7-10 Aug. 2011, Seoul, 2011

25. Thank you