Front End and Custom Hardware

1. Front End and Custom Hardware Ed Jastrzembski (Data Acquisition Group)

2. Outline • Trigger Supervisor System • Data Acquisition/Triggering • General Purpose I/O & Signal Handling • Other Useful Modules • F1TDC Module • New Projects (DAQ = Data Acquisition Group, FEG = Fast Electronics Group)

3. TS Functions • Central control point for acquisition activity • Accepts and prescales multiple sources of triggers • Maintains system busy while an input trigger is being processed • Generates signals used for the gating and timing of front-end electronics • Coordinates the actions of multilevel trigger systems • Communicates triggering information to the system’s readout controllers • Keeps track of the number of events currently in the front-end module buffers

5. TS Facts Level 1 Trigger Inputs 12 Prescalable Level 1 Inputs 8 Prescale Factors Inputs 1-4 24 bits Inputs 5-8 16 bits Prescale Input Bandwidth > 60 MHz Level 1 Trigger Coincidence window 7-100 ns Delay (Trigger to Level 1 Accept) 40 ns (min) Level 1 Accept Jitter (RMS) <35 ps Maximum Event Rate 3 MHz TS-ROC Communication RS-485 parallel, Full handshake Programming Interface A24/D32 VME slave Form Factor ‘D’ size VXI (340 x 367 mm)

7. TS Features (Version 2) • All I/O differential ECL • 6-bit trigger type communicated to ROCs • New trigger mode – All L1 Accept signals may be driven promptly (~10 ns) after L1 Trigger • Programmed Events - 2 special event types are defined and can be triggered by software or an external signal. These events are guaranteed to be sent to the ROCs. (No L1 Accept or L2 Start signals are issued for these.) • Latched Triggers – 12-bit pattern stored in a FIFO for readout. Also driven off the board promptly for use in a Level 2 trigger. • Onboard VME Trigger Interface – allows crate containing TS to be read out on an event-by-event basis without additional hardware. • Additional monitoring of ROC branches – e.g. # events in each ROC branch buffer • Scalers: 12 L1 Trigger inputs Accepted events 6 programmable Pair count a 200 kHz clock, one gated by TS Live –> Livetime estimate

8. Trigger Interface • Supplies trigger information (event type ) to ROC • Presence of trigger data communicated to ROC by interrupts or polling. • TS Mode – for multiple ROC systems. Trigger data (8 bits) is on branch cable driven by TS. Each ROC acknowledges (through interface) the receipt of data from TS. • External Mode – for single ROC systems. Accepts several free running trigger streams. Latches up on trigger, issues L1 Accept, maintains busy until ROC handles event (non-buffered). • Other features – 8-bit output port always available. When in TS mode external trigger inputs can be used as an input port. • Types: • Fastbus – Fastbus Auxiliary Card for the SFI Fastbus ROC • 4 external trigger inputs + 2 data levels (differential ECL) • VME – 6U VME module for a VME ROC (single board computer) • 4 external trigger inputs + 8 data levels (differential ECL)

9. Fastbus Signal Distribution Module (FEG) • Distributes timing and gating signals to Fastbus modules through the Terminated Restricted (TR) bus lines • Plugs into the rear of the Fastbus backplane

10. TS Transition Module • Interface between TS and front end electronics • Generate and distributes ADC gates, TDC starts/stops, and control signals (ADC 1881, TDC 1875, TDC 1877) • Allows retiming of TS L1 Accept signal to L1 Trigger signal in generating gates, starts/stops • Cables directly to Fastbus Signal Distribution Module on Fastbus backplane • Supports up to 7 Fastbus crates • Permits coupling and uncoupling of dual TS systems (e.g. TS in each spectrometer arm)

12. VME Latch FIFO • 16 digital data inputs sampled (differential ECL) • 32K deep buffer (simultaneous read/write) • Can be configured to automatically buffer data after sampling, or wait for an input control signal (Buffer) to initiate storage (useful for multiple level trigger systems). • Strobe mode – inputs are sampled on the rising edge of the Strobe control input • Latch mode – if a data input is asserted at any time during the window defined by the Gate_In control input, the corresponding data bit will be set. • Gating signal of adjustable width can be generated on board from the Strobe input and fed back to the Gate_In input. • Narrow pulses (2 ns) can be detected (ECL logic) • Can generate a VME interrupt when the number of data words stored is equal to a value programmed by the user.

13. VME Latch Driver • 16 digital data inputs sampled (differential ECL) • Sampling modes same as VME Latch FIFO, but no buffering or readout • Drives out (differential ECL) two copies of latched data pattern along with Output_Ready control signal • Control signal protocol compatible with ECLine logic (LeCroy) • Narrow pulses (2 ns) can be detected (ECL logic) • Useful to set up data for subsequent logic (e.g. Level 2 trigger)

14. VME Memory Lookup Unit • 16 inputs x 16 outputs (differential ECL) • For each output, any logic function of the 16 inputs can be defined. • Input data is stored in registers on the rising edge of the Input_Enable signal and presented to the memory as an address. • Rising edge of Input_Enable negates Output_Ready signal until valid data is driven from the module (ECLine protocol) • Fast – Input_Enable to Output_Ready < 25 ns • Pulse Mode - Outputs can be configured (in groups of 4) to drive out programmed levels for a time interval (10 – 100 ns) after which the outputs are negated.

15. Final Stage of CLAS Level 2 Trigger Logic

16. VME Programmable ‘OR’ Module • 32 digital inputs (differential ECL) • Each input can be enabled or disabled from contributing to the output. • The output is the logical ‘OR’(1-32) of all enabled inputs. • Additional outputs – ‘OR’(1-16), ‘OR’(17-32) (enabled inputs only) • Output flavors – differential ECL, single-ended ECL, NIM(1-32) • Fast – delay < 10 ns, with low jitter – suitable for trigger applications • The state of all inputs can be read at any time.

17. VME Flexible I/O Module • Modular I/O system • Base board – contains VME interface + registers (‘complex’) • Plug-in cards – produce desired I/O levels (NIM, ECL, TTL,…) and connectors (Lemo, BNC,…) (‘simple’) • Base board – has two 16-bit ports, each with its own Data Register & Control/Status Register (CSR) • Plug-in cards – defined to be either of type Input or Output. • Base board recognizes Plug-in card type and configures itself to communicate with it.

19. Input Card Functions • Latch inputs on VME read • External latch mode – an External Strobe signal latches the input values and sets a bit in the CSR to indicate data is available. A VME interrupt may also be generated. • Output Card Function • Direct VME output – outputs are maintained until next VME write • VME Pulsed output – data written to the port’s Data Register sets a 16-bit enable mask. Enabled channels are pulsed when a CSR bit is written. • External Strobe output – data written to the port’s Data Register sets a 16-bit enable mask. Enabled channels are copies of the External Strobe input. • Existing Cards (16-bit, I & O) • Differential ECL, single-ended ECL, NIM

20. Specialty Plug-in Cards – use base board as a programming interface to configure the circuit on the card – Random Pulse Generator (FEG) - internal reference source programmable (2 Hz – 200 kHz) - can select external reference source - 2 independent channels - NIM, ECL outputs – Majority Logic Unit (FEG) - 6 inputs - NIM I/O

21. Carrier Card ‘Standard’ • Mechanical and electrical ‘standard’ for circuit boards • With the appropriate Carrier Card, such a circuit can be installed and function in a NIM chassis, VXI chassis, or VME chassis. • Existing Circuits • NIM  ECL (differential) • NIM  ECL (single-ended) • ECL (differential)  ECL (single-ended) • ECL (differential)  RS-485 • Fan outs – ECL (differential), ECL (single-ended)

24. VME FIFO Memory • Input Port – Front panel 32-bit parallel data, RS-485 differential receivers. Allows multiple sources of data to be linked to one memory. Maximum input rate is 40 MB/s (pipelined mode). • Memory – 128k x 32 bit FIFO (simultaneous read/write). FIFO is also writable from VME. (Upgradeable to 256k x 32 bit). • Output Port – VME 64-bit block transfers. Output transfer rate is > 50 MB/s. • Control Features – Total Word Count, Event Counter, Event Word Count FIFO, Programmable Almost Full Flag, Interrupt Capability.

25. Fan Out Modules (differential ECL I/O) • VME ( 1  2 ) x 16 (FEG) • Camac ( 1  2 ) x 16 (FEG) • Camac ( 1  2 ) x 16 (FEG) • Programmable output pulse widths • Carrier Card Circuit • Selectable • ( 1  2 ) x 12 • ( 1  8 ) x 3 • ( 1  12 ) x 2 • ( 1  24 ) x 1

26. VME Remote Monitor/Reset Module (FEG) • Remote monitoring of VME crate voltages and user input signals (3) • Remote reset of VME crate by asserting bus signal Sysreset* • Host computer or terminal server communicates with multiple modules via a daisy-chained RS-232 link. • Each module is programmed with a unique name – system supports up to 256 modules. • Long-distance transmission done differentially through a pair of translators (RS-232  RS-485). • 2 versions – normal VME slot, or rear plug-in (saves slot)

27. VME Discriminator/Scaler (FEG) • 16 channels – for PMTs • x4 gain amplifier on analog inputs • Amplifier/discriminator circuitry on socketed modules (4 ch/mod) • Common threshold & output pulse width (programmable) • Differential ECL outputs • Two 32-bit scalers assigned to each channel. • External signal Gate1 gates scaler 1 of all channels. • External signal Gate2 gates scaler 2 of all channels.

28. JLab High Resolution TDC(DAQ + FEG)

29. F1 TDC Chip • Designed at the University of Freiberg for the COMPASS experiment at the CERN SPS • COMPASS (COmmon Muon Proton Apparatus for Structure and Spectroscopy) • Used for many different COMPASS detector systems (straws, dc, muon, mwpc, scifi, hodoscope…) • In most cases the F1 chip is mounted on the COMPASS detector system, so reasonably low power consumption was an important design consideration • Marketed by acam-messelectronic gmbh (Germany) • Uses purely digital delay techniques to measure time • Stability ensured by self adjustment of core voltage through a PLL circuit and external voltage regulator

30. F1 Chip Features • 8 channels @ 120 ps LSB (normal resolution mode) • 4 channels @ 60 ps LSB (high resolution mode) • 16-bit dynamic range – 7.8 us @ 120 ps LSB, 3.9 us @ 60 ps LSB • Multihit – buffers allow the storage of up to 16 hits/channel (32 for high resolution mode) • Trigger Matching – allows for the selection of hits within a programmable time window and latency from the trigger signal • Trigger buffering – up to 4 triggers may be stored for processing • High rate capability – for trigger rates < 625 kHz, input hit rates > 4.4 MHz (normal resolution) or 7.2 MHz (high resolution) are possible

31. Trigger Matching Procedure

32. TDC Module Features • 64 channels normal resolution, 32 channels high resolution • 6U single slot VME64x slave – differential ECL inputs • 128K word deep FIFO buffer for each F1 chip • VME interface (64 bit) and control logic in a single FPGA • FPGA has an internal 512 x 64 bit FIFO buffer • Data from multiple chips that are associated with the same trigger are assembled into an event fragment • Module can interrupt crate controller when a programmable number of event fragments are available • A set of TDC modules may be read out as a single logical read using a multiblock protocol (token passing) • On-board storage (non-volatile) and auto-loading of F1 chip configuration data

33. JLab TDC Module – Top & Bottom Sides

34. Timing distribution for an input signal that has a fixed time relationship to the Start signal. Unfolding the uncertainty of the input signal (33 ps) from the measured distribution yields a resolution (RMS) of 61.2 ps.

35. Timing distribution for an input signal that has a fixed time relationship to the Start signal. Unfolding the uncertainty of the input signal (33 ps) from the measured distribution yields a resolution (RMS) of 86.2 ps.

36. Transfer function for the TDC in high resolution mode.

37. Residuals for the linear fit of the transfer function of the TDC in high resolution mode. Note that one TDC channel (bin) corresponds to about 0.06 ns.

38. Resolution across the TDC dynamic range (high resolution mode).

39. Resolution as a function of trigger rate (high resolution mode).

40. F1 TDC Control Signal Fan Outs • CLOCK, SYNC_RESET, START, TRIGGER • Front Panel Fan Out • Supports 5 TDC boards (can be cascaded) • On-board oscillator, software generated SYNC_RESET • Program to select internal/external oscillator, SYNC_RESET • 6U VME64x card • (out for manufacture) • Back Panel Fan Out (FEG) • Supports 20 TDC boards • On-board oscillator • Jumper select to use internal/external oscillator • Rear card cage mount for VME64x crate • (in design)

41. 64-channel ADC/DAQ System (FEG) • Designed for use in medical imaging instrument (Detector Group) • Modular architecture – four 16 channel ADC modules • Individual Channels are self-triggering • Time-over-threshold discriminator • Integration of input pulse (delayed) is active during time-over-threshold • A 2.5 MHz 12-bit ADC samples after integration • Baseline subtraction • Filtering: (min,max) charge, (min,max) pulse width • 5 ns resolution time stamp allows correlation of data between channels • Deep Multi-level buffering • Global Front-end inhibit • Readout with high-speed USB2 interface (10 MB/s) • (in design)

42. Pipelined ADC (DAQ,FEG) • 10 bit resolution @ 250 MHz sampling rate (chip currently ‘exists’) • Can trade off increased resolution for slower speed • 16 channels on 6U VME board • ADC continuously samples input and writes to a circular buffer • (buffer depth x 4 ns > trigger latency) • Trigger causes module to look back in the buffer (trigger latency) and copy an appropriate window of data to output buffer for readout. • Module may optionally integrate data, extract leading edge timing (~1 ns), and write these to the output buffer.

43. Hall D • For each sample, the module sums ADC outputs of all channels and integrates this sum over a time period (sliding window). • This quantity would be added externally for multiple boards (real time energy sum) and used in the Level 1 Trigger. • Board in concept stage • Think about your requirements

44. END

45. (Spares follow)

46. Data AcquisitionFast Electronics D. Abbott F. Barbosa E. Jastrzembski C. Cuevas J. Proffitt J. Wilson

47. F1 TDC Block Diagram

48. TDC Module Block Diagram

49. VCO for a fine- and coarse-time digitizing circuit

50. PLL based on an asymmetric ring oscillator and phase and frequency stabilization. PLL frequency is adjusted by the low (N) and high (M) frequency dividers.