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FRONT-END and HV

FRONT-END and HV

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FRONT-END and HV

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  1. FRONT-END and HV • System architecture: brief summary • Status of chips production • Front-end board for the wire-chambers: status • First prototype of front-end board for GEMs • Tests performed • Front-end chip for GEMs • Radiation hardness • Organisation and responsibilities • Grounding issues • HV Walter Bonivento - INFN Cagliari

  2. The LHCb muon electronics project • Common project with wire chambers: • same far-end structure • same front-end board conception: 2 CARIOCA chips + 1 DIALOG chip • same bids and producing companies • same people • BUT • CARIOCA  CARIOCA GEM • front end board (CARDIAC) of different size and layout • SPB integrated on the CARDIAC • different cables and connectors space requirememnts Walter Bonivento - INFN Cagliari

  3. 8 PCH 8 PCH ASD ASD SERVICE board (on crates) I2C MASTER LOW VOLTAGE CONTROLS CALIBRATION PULSES OFF DETECTOR ELECTRONICS SYNCHRONIZATION TIME (PHASE) MEASUREMENT DATA FORMATTING DATA TO MUON TRIGGER Counting Room DATA TO DAQ RECONSTRUCTION System architecture Triple_GEM det b Triple_GEM det a F/E board ON DETECTOR ELECTRONICS DIALOG 8 LCH 10m cabling (LVDS) Walter Bonivento - INFN Cagliari

  4. CARIOCA At Cdet=15-30pF, tr=8ns, Zin=50Ω, ENC=0.5-0.6fC linear up to 200fC VERY SIMILAR CHARACTERISTICS TO ASDQ All differential circuitry, unipolar shaping DC coupled active BLR (CERN + CBPF Rio) shaper, 2pole-zero ion tail cancellation IBM 0.25 μm radiation tolerant technology 8 analog input channels 8 LVDS output channels gain about 12mV/fc @ Cdet=15-30pF Discriminator threshold can be individually set to compensate for offset from process variation internal test structure to inject signal from DIALOG to CARIOCA input; minimum injected charge 50fC only checks if channel ON/OFF Walter Bonivento - INFN Cagliari

  5. DIALOG IBM 0.25 μm radiation tolerant technology 16 LVDS input channels 8 LVDS output channels INFN -CA • generates logical channels by OR-ing of two face-to-face physical channels • provides a masking facility to access single channels • threshold DAC and line drivers for the CARIOCA chip • integrates 16 8-bit DACs with output buffer to set the CARIOCA discriminator threshold with about 0.17fC granularity • Programmable delays 31 steps of 1.6ns 50ns max • Digital shapingoutput signal width 8 steps of 3ns 25ns max • Front-end rate and noise monitor 16 24-bits rate counters • all functionalities can be controlled via I2C interface • Triple-voted and auto-corrected register for better SEU immunity Walter Bonivento - INFN Cagliari

  6. Chip NRE run submission Submitted in September, Wafers Received in November, Packaged circuits to be delivered next week RETICULE: 4 CARIOCA, 2 DIALOG, 1 SYNC 1 CARIOCAGEM. Reticule size 15.3 x 8.1 mm2 Reticules/wafer ~ 205  Chips per wafer: 820 CARIOCA, 410 DIALOG, 205 SYNC, 205 CARIOCAGEM Walter Bonivento - INFN Cagliari

  7. Wire chamber front-end boardsCARDIAC 63mm More extensively tested 50mm final DIALOG final CARIOCA D C C CARDIAC 2.0 on wire-chamber power consumption 0.5A 1.25W 6 layers: signal, GND, LV, signal,GND,signal Walter Bonivento - INFN Cagliari

  8. Experience with CARDIAC 2.0 • CARDIAC • About 20 boards of CARDIAC 2.0 produced and tested • Good experience now with the PVSS/CANBUS system (Rome I) to communicate with and program the DIALOG chip via I2C bus • Many measurements in the Lab (Cagliari and Potenza-Rome1): performance almost OK Walter Bonivento - INFN Cagliari

  9. Experience with CARDIAC 2.0 Test at GIF (CERN): fully equipped M3R2 wire-chamber 12 CARDIAC boards: 2 I2C long lines chains and 1 SB controlled via CANBUS by a PVSS program The same number of I2C lines as for triple-GEM chambers!!! Study of the efficiency and time properties to test: - the front-end electronics reliability; - high rate on the chamber The tests were completely satisfactory Walter Bonivento - INFN Cagliari

  10. The front end board for GEMs: CARDIAC GEM • CARDIACGEM 1.0 : a very first prototype  3 boards assembled • Tight space requirements  45x70mm length and 14mm thichkness • Two boards in one: FEB+SPB • Spark protection on the bottom; the 3 chips on the top • Spark protection circuit: only 500V  simplified  two resistors+2 double diodes -> to be tested (the one of WPC well tested) • New type of connectors and cables pitch reduced by half • need a special cable 0.635mm pitch I2C LV 45mm LVDS 70mm bottom top Walter Bonivento - INFN Cagliari

  11. How the board is plugged in Minimum space available on the top for cables 5-6mm Walter Bonivento - INFN Cagliari

  12. Lab tests of CARDIAC (-GEM) Standard lab tests (also at the Company assembling the boards) ENC~05-06fC; not depending on channel position gain curve S-curve Cdet=15pF Problem: due to process variations spread in gain curve parameters: a)SLOPE b) INTERCEPT If one threshold value for all channels is set, then about 1fC rms effective threshold spread is obtained too much for GEMs (we want to trigger at ~2-2.5fC) remember: WPC trigger at 6-7fC much less of a problem… Walter Bonivento - INFN Cagliari

  13. Lab tests of CARDIAC (-GEM) (II) • STRATEGY to reduce the threshold spread: • measure noise counts vs. TH curve • correct for the intercept spread in two ways: • a) equalising minimum thresholds(>0!! in this chip) • b) equalising noise count values y~erfc(x) effective threshold spread is reduced to about 0.5fC(a) or 0.7fC(b) rms This can be done in LHCb and continously monitored! Walter Bonivento - INFN Cagliari

  14. Lab tests of CARDIAC (-GEM) (III) • A further improvement of the threshold spread (reducing it to ~0fC) • can be obtained in the lab: • measuring directly the gain at the assembling company and keeping a database (foreseen in the contract) • ΔG/G(%)=0.5x ΔT(0C) • =20mV of power supply • the same cannot be done for the intercepts since e.g. • ΔG/G(%)= 1mV of power supply!!! • 20mV in supply voltage moves the intercept by 20% !!!! •  the slope is much less sensistive than the intercept to supply voltage variations •  we are lucky that the intercept spread can be compensated for with the other method… • 2) injecting a calibration pulse on G3down (to be tested) Walter Bonivento - INFN Cagliari

  15. Lab Test with GEM chamber (HV off) Very preliminary test Count rates on 3 chambers with ~3fC threshold below a kHz (most channels << 1kHz) NB: cables to be replaced, no FC, simplified GND… Walter Bonivento - INFN Cagliari

  16. Why CARIOCA GEM and how Two main reasons: 1)minimum threhsold: in beam tests with ASDQ it was set to 2fC; with CARIOCA10 the minimum is 2.5-3.3fC 2) due to ion tail cancellation in the CARIOCA shaping circuit afterpulses • 10-15 V loss in plateau with CARIOCA Walter Bonivento - INFN Cagliari

  17. The triple-GEM detector signal Primary ionisation and drift Signal formation: same as pulse mode ionisation chamber 5 ionisation clusters 1 ionisation cluster Example: 5 primary cluster signal Walter Bonivento - INFN Cagliari

  18. signal shapes SPICE CARIOCAGEM (m.i.p. signal) CARIOCAGEM δ CARIOCAGEM (1cl) CARIOCA10 δ CARIOCA10 (1cl) CARIOCA10 (m.i.p. signal) Walter Bonivento - INFN Cagliari

  19. Afterpulses with ion tail cancellation two reasons: 1) undershoot blow up blow up simulation 2) inside the event: different gain of clusters irreducible fraction of afterpulses 10%-15% Walter Bonivento - INFN Cagliari

  20. FEB Production test strategy • Tests of the produced chips will be performed by the same company performing sawing and packaging • Five company already contacted (Microtest, Microtec, DELTA, Edgetek, HCM). Order procedure is under preparation. • This is sure in the case of DIALOG and SYNC. Concerning CARIOCA still some discussion (interest of CBPF – Rio + Brazilian company). Decision to be taken in the next two weeks. • FEB production testcompany with a tool developed • by INFN RomaI @Potenza Walter Bonivento - INFN Cagliari

  21. Next steps • CARDIAC-GEM 1.1 under design: some changes (cross-talk improvements)it will have CARIOCAGEM • same bids and orders as CARDIAC • Order for final PCB production placed • Gerber files not yet sent • Tender for board assembling + testing (with equipment provided by Rome I+PZ group) started order placed in ~1.5months • some pre-production expected first(50 boards) and after measurements the rest of the boards Walter Bonivento - INFN Cagliari

  22. Radiation hardness • Total dose in M1/R1: 500 kRad in 10y • Both chips 0.25μn CMOS rad tolerant design • no digital circuitry • 2 chips of a previous version tested for total dose up to 10MRad •  sensitivity decrease < 3.5% • sensitivity spread unchanged •  threshold moved by 10-20mV (1fC) • tested for total dose up to 1MRad with 60Co source • tested for SEE @ PSI 250 MeV p; flux=6x108cm-2s-1 • without activating self correction #SEE<1 in 10 days • for total fluence of 1013 p/cm-2 (10 LHCb years in M1/R1) CARIOCA DIALOG Walter Bonivento - INFN Cagliari

  23. Grounding • The proposed grounding scheme follows the one of WPC and requires : • FC as detector signal ground reference • Floating low voltage power supply • Chamber connected only to the safety ground • I2C ground broken by 100KΩ resistor on FEB • LVDS GND not connected; all GNDs put together at FE racks • LVDS cable shields connected to GND at the rack side Walter Bonivento - INFN Cagliari

  24. LV So far LV distribution was performed with LV boards placed on the chamber with non rad tolerant regulators in LHCb we have to go to rad tol regulator(STM-CERN design) same as for LHCb wire-chambers boards were fed with LV from a min-bus (not in series!) • Power consumption/board=0.5A • Supply voltage =2.5V • #boards =24/chamber • #boards/rad tol regulator=3; • #rad tol regulators/chamber=8; some prototype boards for WPC exist engineering for GEM (tight clearance!) under design Walter Bonivento - INFN Cagliari

  25. 50 KW 50 KW 2.2 nF 1MW 5 KW 5 KW 10 nF g1 220 KW 175 KW g2 210 KW 810 KW 5 KW 5 KW 10 nF g3 63 KW 75 KW HV: a resistive divider chain So far: 7 HV channels/gap: the easiest and the most expensive but very dangerous in case of a trip at least the GEMs should be together divider monitorof 3-GEM current ! 1)6kV/1mA • Requirements: • stay in plateau with 10 μA in the detector in LHCb • limit power consumption • protect GEMs in case of sparks • monitor current in the detector •  a candidate solution with 3dividers and 3 commercial power supplies (CAEN) /sector 2)4kV/2mA total Power consumption 15 W at plateau end 3)1.3kV/10mA ΔVgem2 Prototype of Al2O3 with dissipating bottom layer and trimmed serigraphed resistors under design Walter Bonivento - INFN Cagliari

  26. Resistive divider chain: SPICE simulation SPICE simulation based on measurements from our group: see TNS 49(2002)1638 voltage drop ΔVsum SPICE simulation based on measurements from our group: see TNS 49(2002)1638 8V ΔV1,2,3 ΔV1,2,3 spark plateau 1280V to 1350V • Effect of a spark: HV recovery time • main sector • neighbour sector 5ms Walter Bonivento - INFN Cagliari

  27. Test of the divider chain in the lab • LHCb divider chain designed to have minimal drop • To test our simulation a divider was built with 10k larger value resistors • (standard HV – CERN store) than what we need in LHCb • much larger drop Two radioactive sources Sr and Ru Four readings: • I(pad)  1 to 2.3μA (0.5 LHCb!!) • I (power supply divider) 180μA • I(power supply cathode) 0.3-0.7μA • ΔV on the 3rd GEM where the maximum drop is expected 3-5V agreement with simulation within 50% (in the LHCb version we expect 5%OK!!) more tests with x-rays to come Triple-GEM chamber 10x10cm2 cathode independently fed with HV one divider Walter Bonivento - INFN Cagliari