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Integrated Test Data Compression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing

Integrated Test Data Compression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing. Nicola Nicolici Electrical and Computer Engineering. Paul Theo Gonciari Bashir Al-Hashimi Electronic Systems Design Group. University of Southampton, UK. McMaster University, Canada.

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Integrated Test Data Compression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing

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  1. Integrated Test Data Compression and Core Wrapper Design for Low-Cost System-on-a-Chip Testing Nicola Nicolici Electrical and Computer Engineering Paul Theo Gonciari Bashir Al-Hashimi Electronic Systems Design Group University of Southampton, UK McMaster University, Canada

  2. Overview • Low-cost system-on-a-chip test • Single vs. multiple scan chains compression • Proposed add-on architecture • TAM add-on architecture • Core wrapper design • Reduce control and area overhead • Design flow integration • Experimental results • Conclusion

  3. Low-cost SOC test • Problems • High volume of test data • Increased chip/ATE frequency ratio • Increased chip/ATE pin number ratio • Increased scan-power dissipation High ATE costs and yield loss

  4. Low-cost SOC test • Solutions • Test data reduction • Reuse existing ATE technology • Exploit chip/ATE frequency ratio • Reduce pin count testing (RPCT) • Scan chain partitioning

  5. SOC Core Core TAM add-on TAM add-on architecture Low-cost solution for core based SOC test

  6. Overview • Low-cost system-on-a-chip test • Single vs. multiple scan chains compression • Proposed add-on architecture • TAM add-on architecture • Core wrapper design • Reduce control and area overhead • Design flow integration • Experimental results • Conclusion

  7. counter Single scan chain TDC SOC 5 FF sync s i decoder Core ATE Head s o SISR

  8. Single scan chain TDC (cont) • Exploit test set regularities (e.g., runs of 0s) • Based on coding schemes • Exploit frequency ratio • Synchronization overhead – temporal deserialization [Gonciari, ETW02] • External clock synchronization • FIFO like structures • High scan power due to the long scan chain

  9. Multiple scan chain TDC ctrl SISR XOR Network scan chain scan chain scan chain WSC scan chain Core Core data in

  10. Multiple scan chain TDC (cont) • Exploit care bits sparseness • Uses XOR based spreading networks • Temporal pattern lockout • Extra control line • Doubles the volume of test data • Influences test application time • Structural Pattern lockout • can influence fault coverage • High scan power due to driving of all scan chains Extend single scan chain TDC to multiple scan chains

  11. scan chain scan chain decoder shift register scan chain Core Extend single scan chain TDC … Use one decoder and shift register [Chandra, DATE02]

  12. Use one decoder and shift register • Loosened the ATE timing constraint • Exploitation of frequency ratio • Reduce peek scan-power • Shift register buffering • Synchronization overhead • Decrease in compression ratio • Unbalanced scan chains • Test set rotation

  13. distr dec1 scan chain ctrl ctrl ctrl dec2 scan chain dec3 scan chain Core Extend single scan chain TDC … (cont) Use one decoder per scan chain [Chandra, TCAD01] [Gonciari, ETW02]

  14. Use one decoder per scan chain • Loosened the ATE timing constraint • Exploitation of frequency ratio • Reduced scan-power • Scan chain partitioning • Good compression ratio • No test set rotation • Reduced synchronization overhead Increased area and control overhead Large number of scan chains Unbalanced scan chains

  15. Low-cost SOC test • Solutions • Test data reduction • Reuse existing ATE technology • Exploit chip/ATE frequency ratio • Reduce pin count testing (RPCT) • Scan chain partitioning Use one decoder per scan chain Increased area and control overhead Large number of scan chains Unbalanced scan chains

  16. Overview • Low-cost system-on-a-chip test • Single vs. multiple scan chains compression • Proposed add-on architecture • TAM add-on architecture • Core wrapper design • Reduce control and area overhead • Design flow integration • Experimental results • Conclusion

  17. SOC Core Core TAM add-on TAM add-on architecture Low-cost solution for core based SOC test

  18. Core wrapper design tb1 WSC1 tb2 WSC2 tb3 WSC3 tb4 WSC4 Core • Why core wrapper design ? • WSC partitioning [Gonciari, VTS02] • Useless memory reduction • Easy control

  19. distr dec1 WSC dec2 ctrl ctrl ctrl ctrl WSC dec3 WSC dec4 WSC Core Reducing control and area overhead Instead of

  20. Reducing control and area overhead … • WSC partitioning • 2 partitions • 1 control unit per partition • 1 decoder per partition WSC WSC WSC WSC Core Exploit WSC partitioning for area and control reduction

  21. Reducing control and area overhead … • Control • Length of max scan chain • No of scan chains • Diff of partitions length diff WSC no WSCs WSC WSC WSC length Easy control per partition

  22. length no WSCs scan clk dec diff dec1 WSC data WSC Extended decoder (xDec) – input

  23. no WSCs dec WSC mux SISR WSC Extended decoder (xDec) – output

  24. xDec1 WSC SISR mux WSC mux distr xDec2 WSC SISR mux WSC Core Extended distribution architecture xDistr

  25. WSC WSC WSC WSC WSC WSC WSC WSC Core Core Extended distribution architecture … Unequal partition size for some cores !!

  26. WSC WSC WSC WSC WSC WSC WSC WSC Core Core Extended distribution architecture add-on-xDistr xDec1 mux mux xDec2 mux

  27. Multiple TAM SOC test Core Core add-on 2xSISR Core Core add-on 2xSISR SOC

  28. Design flow integration

  29. Overview • Low-cost system-on-a-chip test • Test data reduction • Synchronization overhead • Single vs. multiple scan chains compression • Proposed add-on architecture • TAM add-on architecture • Core wrapper design • Reduce control and area overhead • Design flow integration • Experimental results • Conclusion

  30. Minimum VTD vs. equal partitions Test bus = 16 Frequency ratio 2

  31. Minimum VTD vs. equal partitions Test bus = 16 Frequency ratio 4

  32. add-on-xDistr vs. SSC Core s35932 Frequency ratio 2

  33. add-on-xDistr vs. SSC Core s35932 Frequency ratio 4

  34. add-on-xDistr vs. SSC System 1 Frequency ratio 2 Test bus 24 Reduction 19.29%

  35. add-on-xDistr vs. SSC System 2 Frequency ratio 2 Test bus 24 Reduction 26.88%

  36. Conclusion • Low-cost solution for core based SOC test • TAM add-on architecture • Design flow integration • Exploited core wrapper design features • Reduced control overhead • Reduced area overhead • Reduced scan power through partitioning • Small area overhead (3-4%) for System1,2

  37. SOC ATE dec SO Head CUT DIB Test data reduction • Aims • Volume of test data • Area overhead • Test application time

  38. sync scan clk CI data in ATE Data out ate clk PG Generic on-chip decoder • Serial decoder • PG and CI can not work independently • Implicit communication between PG and CI • Parallel decoder • PG and CI can work independently • Explicit communication between PG and CI

  39. Synchronization overhead • Extensions to the DIB • Multiple ATE channels • Deserialization units • Latency FIFOs • Clock synchronization

  40. SOC ATE SO dec CUT DIB Synchronization overhead (cont) • New ATEs • Source synchronous buses • Require programming

  41. SOC ATE SO dec CUT DIB Synchronization overhead (cont)

  42. SOC ATE SO dec CUT DIB Synchronization overhead (cont) • Low-cost test through ATE reuse • Small area overhead increase • Solution for entire chip test • Test application time reduction

  43. a = 2:1 0 1 2 3 4 5 6 7 ATE clk CI STOP CI CI Chip clk PG PG PG Synchronization overhead • Old ATEs • Latency FIFO • Clock synchronization

  44. a = 2:1 0 1 2 3 4 5 6 7 ATE clk CI STOP CI CI Chip clk PG PG PG On-chip SO solution

  45. a = 2:1 0 1 2 3 4 5 6 7 ATE clk CI DUMMY CI CI Chip clk PG PG PG On-chip SO solution (cont) • Increased VTD and TAT • Exploit DUMMY bits and reduce VTD and TAT

  46. a = 2:1 0 1 2 3 4 5 6 7 ATE clk CI1 CI2 CI1 CI1 Chip clk PG1 PG2 PG1 PG1 distr dec1 dec2 On-chip SO solution (cont) • Distribution unit • Any number of cores • Self synchronous architecture

  47. XOR-network %tpl

  48. S38417: VTD / TAT for w = 32

  49. S35932: VTD / TAT for w = 32

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