System-on-Chip (SoC) Testing

1. System-on-Chip (SoC) Testing An Introduction and Overview of IEEE 1500 Standard Testability Method for Embedded Core-based ICs

2. What is a SoC? • Technological advances allow electronic systems that earlier occupied one or more boards onto a single IC. The attending advantages are: • Higher performance • Lower Power consumption • Smaller volume and weight • Typically, heterogeneous, containing a mix of: • Digital logic • Memories of different formats and types • Analog circuits • Embedded cores

3. What is a core? • Large, reusable building blocks • Reuse speeds up design, brings in external expertise. • Typical core functions: • CPUs and DSPs • Serial interfaces • Modules for interconnect standards, e.g. PC, USB, IEEE 1394 (Firewire), and for graphics computation, e.g. MPEG and JPEG • Memories • Core Types: • Soft (RTL code) • Firm (netlist) • hard (layout)

4. Core Providers vs. Core Users • Cores have changed the nature of components used in system design: • In traditional system-on-board design provided components were ICs, designed, manufactured, and tested by the provider. Users could assume components to be fault-free and needed to test only interconnect between the components. • In SoC, components are cores (soft, firm, or hard) that are not yet manufactured or tested for defects.

5. New Testing Issues in SoCs • Core user responsible for manufacturing and testing the SoC • However, this is not possible without the assistance of core provider because core design is hidden for IP reasons. • Typically, core provider assists by delivering pre-defined tests with the core. • The problem that faced the SoC designer was how to apply these tests at the core boundaries.

6. IEEE 1500 Standard for Embedded Core Test* • Stated Purpose: Reduce test cost through improved automation, promote good design-for-test (DFT) technique, and improve test quality through improved access. • Scalable standard architecture for test reuse and integration for embedded cores and associated circuitry. • Only defined for digital circuitry. • Has serial and parallel test-access mechanisms (TAMs) and an instruction set for testing cores, SoC interconnect, and circuitry. • Provides features to isolate and protect cores • http://grouper.ieee.org/groups/1500/index.html. See also, E. J. Marinissen et al., • Journal of Electronic Testing: Theory and Applications (JETTA), 18, 365-383, 2002.

7. Architecture components Source Sink TAMs Wrapper Source/sink can be external or internal to the chip. Generic Test Access Architecture

8. Overview of Wrapper Architecture

9. Wrapper Instructions

10. Timing: WIR shift, then WIR Update

11. Wrapper Boundary Cells For Core Input For Core Output

12. Wrapper Serial Bypass Example

13. Wrapper External Test Mode

14. Core Test Language (CTL) • Purpose: Support all information the core provider needs to give for embedding the core in a SoC. • Requirement: Patterns, which contain bulk of the test data, are reusable without any modification. CTL Components

15. SoC Test Challenges • Core Test • Providing DfT inside cores and test patterns to linked by SoC designer to chip-level test patterns sources and sinks that may be on-chip (BIST) or off-chip (ATE) • Core Test Access: Problems relate to deep embedding of cores and their large I/O pins compared to chip I/O pins. Sophisticated TAMs provide the solution. • SoC Level Test: How to integrate individual core tests and tests for interconnect? The solution take the form of test scheduling strategies.

16. Two Compliance Levels • Unwrapped Cores: Bare core - no wrapper - but must have a CTL program for core test at the bare-core level, which can be used to design a “1500-wrapped” core. • Wrapped Cores: IEEE 1500 wrapper + CTL program.

17. Example Core and Wrapper

18. Instruction Decoding for Serial and Parallel Tests