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System-on-Chip (SoC) Testing
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  1. System-on-Chip (SoC) Testing SoC Wrapper/TAM Design Wrapper/TAM Optimization

  2. Scan Chain Architectures* * J. Aerts and E. J. Marinissen, ITC 1998, pp. 448-457 Wrapper/TAM Optimization

  3. Paper Summary • Given: • # pins SoC available for external scan test • # scan patterns of each core • # scan FFs in each core the paper explores the pros and cons of three possible scan-chain architectures for testing the SoC with external source and sink. Wrapper/TAM Optimization

  4. Three Basic Scan Architectures • Multiplexing: Whole TAM width available to each core, but one at a time. • Daisychain: Long chains across multiple cores simultaneously test multiple cores, bypassing those for which the testing is completed. • Distribution: Test many cores concurrently but by dividing the TAM lines among them. Wrapper/TAM Optimization

  5. Multiplexing Architecture - 1 • Full TAM width available to each core exclusively • DeMux/Mux at inputs and outputs are necessary to connect TAM lines to core pins. • Each parallel scan chain requires two signals: scan-in and scan-out. Additionally, at least two global signals are necessary to control scan-enable and mux/demux Wrapper/TAM Optimization

  6. Multiplexing Architecture - 2 • # scan chains available: where, K = # pins available for scan test M = number of control pins (= 2) • Total test time, overlapping scan-in and scan-out: Wrapper/TAM Optimization

  7. Daisychain Architecture • A 2-to-1 mux after each core selects either the core’s internal scan chain or the (buffered) bypass • One test Strategy: Use daisy chain to transport patterns to all cores at once, until a core runs out of patterns and is bypassed. • Other test strategies are also possible Wrapper/TAM Optimization

  8. Distribution Architecture • Distribute the scan chains over the cores • Each core gets assigned its own dedicated scan chains • The number of scan chains must exceed the number of cores. Wrapper/TAM Optimization

  9. Hybrid Architectures • Test-Bus1: Combines multiplexing and distribution. • TestRail2: Combines daisychain and distribution. • P. Varma and S. Bhatia, ITC98, pp. 294-302. • E. J. Marinissen et al., ITC98, pp. 284-293. Wrapper/TAM Optimization

  10. Test Wrapper and TAM Co-Optimization for SoC V. Iyengar, K. Chakrabarty, and E. J. Marinissen, JETTA 18, March 2002, pp. 211-228 Wrapper/TAM Optimization

  11. Paper Summary • Simultaneous design of wrapper and TAM to optimize the testing times for cores. • Algorithm improves on earlier methods of wrapper design in reducing the TAM width required to achieve optimum test time. • Another enumerative algorithm for TAM optimization for small number of TAMs. Wrapper/TAM Optimization

  12. Example SoCs - 1 (from ISCAS Benchmarks) Wrapper/TAM Optimization

  13. Example SoCs – 2(From Philips Research) Wrapper/TAM Optimization

  14. Unbalanced vs. Balanced Wrapper Chains The time is minimized for balanced cores. Unbalanced Balanced 8 clocks/scan 14 clocks/scan Wrapper/TAM Optimization

  15. Wrapper Design Example without and with Co-optimization Assume: Available TAM Width: 4 4 inputs 2 outputs 4 scan chains: 32, 8, 8, 8 long Clearly, (b) utilizes TAM width better than (a) Wrapper/TAM Optimization

  16. Longest Wrapper Scan-in (Scan-out) vs. TAM Width Problem: Given the following internal scan chain lengths, plot the longest wrapper scan length as a function of TAM width k for k = 1, 2, 3, 4, 5, 6. Given scan chain lengths: 8, 8, 8, 8, 8, 10, 10, 10. Wrapper/TAM Optimization

  17. Example of a Philips’ p93791 core Example Pareto-optimal point • This core has: • 417 functional inputs • 324 functional outputs • 72 bidirectional I/Os • 46 scan chains of lengths: • 7x500 bits • 30x520 bits • 9x521 bits Wrapper/TAM Optimization

  18. Two-Priority Wrapper Optimization Problem: Formal Statement The paper provides an approximation algorithm based on the Best Fit Decreasing (BFD) heuristic to solve the problem. Wrapper/TAM Optimization

  19. Algorithm Wrapper/TAM Optimization

  20. Example Core and Result Wrapper/TAM Optimization

  21. Optimal Core Assignment to TAMs • Test Bus Model for TAM Design: Cores on each TAM are sequentially tested Test Bus Model for TAM Design Multiplexed Cores Cores with Bypass Wrapper/TAM Optimization

  22. Problem Definition Minimize the system test time by assigning cores to TAMs when the TAM widths are known: An integer linear programming (ILP) based algorithm is presented in the paper to solve small instances of the problem. Wrapper/TAM Optimization

  23. Results for SoC from ISCAS Benchmarks -1 Wrapper/TAM Optimization

  24. Generalizations - 1 • The paper goes on to solve the following generalizations of the problems discussed so far: Optimal Partitioning of TAM Widths: Wrapper/TAM Optimization

  25. Generalizations - 2 • Wrapper/TAM Co-Optimization Wrapper/TAM Optimization

  26. Results for SoC from ISCAS Benchmarks -2 Wrapper/TAM Optimization