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Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems. Principal Investigators Jeffrey Vetter, ORNL Robert Schreiber, HP Labs Trevor Mudge, University of Michigan Yuan Xie, Penn State University. Overarching Exascale Motivation.

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blackcomb hardware software co design for non volatile memory in exascale systems

Blackcomb: Hardware-Software Co-design for Non-Volatile Memory in Exascale Systems

Principal InvestigatorsJeffrey Vetter, ORNLRobert Schreiber, HP LabsTrevor Mudge, University of Michigan Yuan Xie, Penn State University

overarching exascale motivation
Overarching Exascale Motivation
  • Small memory capacity has profound impact on other features
  • ‘Feeding the beast’
  • Poor efficiencies
  • Small messages, I/O
blackcomb strategy
Blackcomb Strategy
  • Energy efficiency: NV memories have zero standby power
  • Reliability: MRAM/PCRAM are resilient to soft errors
  • Performance: NVM will be much faster than magnetic disk
  • Identify and evaluate the most promising non-volatile memory (NVM) technologies
  • Explore assembly of NVM technologies into a storage and memory stack
  • Propose an exascale HPC system architecture that builds on our new memory architecture
  • Build the abstractions and interfaces that allow software to exploit NVM to its best advantage
    • Programming support for application-unaware resilience
  • Characterize key DOE applications and investigate how they can benefit from these new technologies
opportunities go far beyond a plugin replacement for disk drives
Opportunities go far beyond a plugin replacement for disk drives…
  • New distributed computer architectures that address exascale resilience, energy, and performance requirements
    • replace mechanical-disk-based data-stores with energy-efficient non-volatile memories
    • explore opportunities for NVM memory, from plug-compatible replacement (like the NV DIMM, below) to radical, new data-centric compute hierarchy (nanostores)
    • place low power compute cores close to the data store
    • reduce number of levels in the memory hierarchy
  • Adapt existing software systems to exploit this new capabilities