CMOL vs NASICs

1. CMOL vs NASICs T. Wang University of Massachusetts, Amherst September 29, 2005

2. Agenda • Problems of pure nanoelectronics • Problems of Nano-CMOS interface • Advantages • Problems • Conclusions on CMOL Teng Wang@Umass

3. Why not Pure Nanoelectronics? • Problems of Nanodevices • Simple devices: Limited functionality • Complex devices: Vulnerable to temperature • Voltage gain<1, signal attenuation • Hybrid Architecture • Nanodevices + CMOS circuits • Interface between CMOS and nanodevices Teng Wang@Umass

4. My Points • FET has the ability to restore signals • Our NASICs are also hybrid Teng Wang@Umass

5. CMOS/Nano Interface • Stochastic assembling: • Limited connectivity • Long time to program • Resistance of interface affects performance • Fabrication issue Teng Wang@Umass

6. CMOS/Nano Interface in CMOL • The key idea is to tilt nanoarray at a certain angle α • Each nanowire can fall on a certain CMOS pin (for addressing) Teng Wang@Umass

7. My Points • sin(a)=Fnano/FCMOS • cos(a)=n* Fnano/FCMOS • (Fnano/FCMOS)2+ (n* Fnano/FCMOS)2=1 • (Fnano/FCMOS)2=n2+1 • Fnano/FCMOS can not be arbitrary. • a must be precisely controlled. • Maybe it can reduce the overhead of CMOS Teng Wang@Umass

8. CMOL Memory • Nanodevices for memory cell • CMOS for coding, decoding, sensing, I/O • Fault tolerance: • Reconfiguration • Hamming codes Teng Wang@Umass

9. My Points • Reconfiguration is an extra assumption. • How to decide the size of block? Teng Wang@Umass

10. Area Efficiency of CMOL Memory • CMOL memory is denser than CMOS memory • Reconfiguration improves fault-tolerance • High yield of single bit is still required. The area per useful bit as a function of single bit yield, for hybrid and purely memories. Teng Wang@Umass

11. My Points • The threshhold of acceptable single-bit yield is too high for current nanotechnology • What’s the yield of total chip? Teng Wang@Umass

12. CMOL Logic Circuits • LUT based FPGA: address decoding and sensing require CMOS circuits. For small LUT, CMOS overhead is great. • PLA based FPGA: • The same problem as LUT-based FPGA • Power dissipation (10KW/cm2) • CMOL FPGA: reconfigurable regular structure Teng Wang@Umass

13. My Points • Why power is so huge? • Most research indicates that nanodevices consume extremely low power: <10W/cm2 Teng Wang@Umass

14. CMOL FPGA – A Single Cell • Logics in CMOS • Interconnections in Nanowires Teng Wang@Umass

15. My Points • Density advantage? Logics in CMOS not nano • How to connect the red/blue terminals with nanowires? Teng Wang@Umass

16. CMOL FPGA – A NOR Gate • Wire-OR logic on nanowires? • NOR is enough for arbitrary logic functions Teng Wang@Umass

17. My Points • Does nanowire have wire-OR/AND property? • 3 CMOS inverter -> a NOR gate? It seems even worse than CMOS. Teng Wang@Umass

18. CMOL CrossNets: Neuromorphic Network • CrossNet is an architecture of neuromorphic network • Somas (in CMOS): Neural cell bodies • Axons and dendrites (mutually perpendicular nanowires) • Synapses (switches between nanowires): control coupling between axons and dendrites Teng Wang@Umass

19. Schematic of CrossNet • Light-gray squares in panel (a) show the somatic cells as a whole. • Signs show the somatic amplier input polarities. • Green circles denote nanodevices forming elementary synapses. Teng Wang@Umass

20. Conclusions • CMOL for: • Memories: reconfiguration, overhead of CMOS • FPGAs: really denser than CMOS? • Neuromophic networks: no comments • Density, delay, power dissipation • Delay should be better than NASIC, since it use a new layer for CMOS. • Power dissipation is hard to compare with NASIC. Teng Wang@Umass

21. Contact us Email: twang@ecs.umass.edu Thank you! Teng Wang@Umass