Lect 6: Protected-Mode SW Architecture II

1. Lect 6: Protected-Mode SW Architecture II

2. TLB (Translation Lookaside Buffer) • maintaining 32 sets of table entries • 128 KB of paged memory are always directly accessible Linear Address Format DIRECTORY PAGE OFFSET 31 22 21 12 11 0 Page Frame Operand Translation lookaside buffer (TLB) Page table entry Page table Page directory entry Page directory table PDBR(CR3)

3. Descriptors and Page Table Entries 23 16 15 8 7 32 0 24 AVL LIMIT 19..16 4 BASE 31..24 G X 0 P DPL S TYPE A BASE 23..16 7 3 SEGMENT LIMIT 15 .. 0 SEGMENT BASE 15 .. 0 0 if data segment (S=1, E=0) Type Field Definition if code segment (S=1, E=1)

4. Loading Descriptor from Descriptor Table 00A0FFFFH GDTR 00A00000H FFFFH 00A02007H GDT (64KB) LDTR descriptor 00A02000H 00A00000H SYSTEM MEMORY 0 82 00 0 90 0090FFFFH 0000 FFFF 00901007H LDT (64KB) CS descriptor 00901000H 2000H LDTR 0090000H FFFFH 00900000H 0 00 FE 60 F USER MEMORY 0000 FFFF 0060FFFFH CODE SEGMENT (1 MB) CS 1005H 0060000H FFFFH 00600000H

5. Protected-Mode System-Control Instruction Set

6. Protection : unauthorized or incorrect accesses of a task’s memory resources Segmentation, paging, and descriptors Segment Level Protection In parallel with address translation Five Protection Checks Type Check: 16 types, Code and Data Limit Check Restriction of Addressable Domain : readable, writeable Restriction of Procedure Entry Point Restriction of Instruction Set Protection and the Protection Model

7. Selector Offset Protection Memory Limit Type and limit check Data Base Access rights Selector Base Limit LDT Limit Base

8. Data Structures contains Privilege Levels CPL : Current Privilege Level DPL of the access rights byte in CS segment descriptor cache register privilege level of the code and data segment for the current task RPL : Requested Privilege Level the privilege level of the new selector loaded into a segment register DPL : Segment Descriptor Privilege Level Privilege Levels Task A local address space Applications Custom extensions System Services Kernel Level 3 Level 1 Level 0 Level 2 Task B local address space global address space Task C local address space

9. Checking: When the selector of a descriptor is loaded into a segment register Restricting Access Data Descriptors : DS, ES, FS, GS, or SS CPL : current privilege level DPL : seg descriptor of the segment containing the operand RPL : requestor's privilege of the selector ; DPL ³ MAX (CPL, RPL) Stack : RPL = CPL

10. Privilege - check 16-bit visible selector Invisible Descriptor CPL CS Target Segment Selector Privilege check by CPU RPL INDEX Data Segment Descriptor 23 16 15 8 7 0 32 24 DPL S TYPE A AVL LIMIT 19..16 4 BASE 31..24 G X 0 P BASE 23..16 7 1 R C A 1 DPL W E 0 3 SEGMENT LIMIT 15 .. 0 SEGMENT BASE 15 .. 0 0

11. Lect 7: Protected-Mode SW Architecture III

12. Intrasegment Jump and Call limit check Intersegment Jump and Call the operand selects the descriptor of another executable segment (Case 1) the operand selects a call gate descriptor (Case 2) Case 1 CPL = DPL or CPL> DPL if the selected code segment is confirming segment Restricting Control Transfers

13. 1 1 2 2 3 Jmp Call Ret 3 E E Jmp Call Ret E Intersegment Intrasegment DPL =1 Conforming Code Seg 1 E 2 E 3 E Calling a Confirming Segment Restricting Control Transfers 16-bit visible selector Invisible Descriptor CPL CS Privilege check by CPU Data Segment Descriptor 23 16 15 8 7 0 32 24 DPL S TYPE AVL LIMIT 19..16 A 4 BASE 31..24 G X 0 P BASE 23..16 7 1 R C A 1 DPL W E 0 3 SEGMENT LIMIT 15 .. 0 SEGMENT BASE 15 .. 0 0

14. Call Gates Trap Gates Interrupt Gates Task Gates Call Gates To define an entry point of a procedure To specify the privilege level required to enter a procedure Gate Descriptors 23 16 15 8 7 0 32 24 DWORD COUNT 4 0 0 0 P DPL 0 TYPE OFFSET 31..16 7 3 OFFSET 15 .. 0 SELECTOR 0

15. JMP nonconforming segment MAX(CPL, RPL) £ gate DPL destination code segment DPL = CPL CALL (JMP instruction to a confirming segment) MAX(CPL, RPL) £ gate DPL destination code segment DPL £ CPL 1 E E 2 G 3 E G Call-gate operation 1 E G 2 G E 3 E

16. OFFSET DPL CNT SELECTOR OFFSET Call-gate operation 16-bit visible selector Invisible Descriptor CPL CS Target Segment Selector Privilege check by CPU RPL INDEX GATE DESCRIPTOR Executable Segment Descriptor 23 16 15 8 7 0 32 24 AVL LIMIT 19..16 DPL S TYPE A 4 BASE 31..24 G X 0 P BASE 23..16 7 1 R C A 1 DPL W E 0 3 SEGMENT LIMIT 15 .. 0 SEGMENT BASE 15 .. 0 0

17. TSS

18. Lect 8: Hardware Architecture of 80386

19. Block Diagram of the 80386 Interfaces of the 80386DX

20. Hardware Organization of the Memory Address Space Physical Memory space : 4GB SW Viewpoint: organized ad individual byte over the address range form 00000000H through FFFFFFFFH HW Organization: No Alignment Interfaces of the 80386DX

21. Bus State and Bus Cycle Bus cycle: minimum two processor clock periods (two bus states: T states) - T1 and T2 T state: a processor clock period (twice the period of the CLK2) Non-pipelined and Pipelined Bus Cycle Non-pipelined Bus Cycle Two T states(T1 and T2) Bus Cycles

22. Pipelined Bus Cycle Bus Cycles

23. Bus Cycles read from memory space locked read from memory space write to memory space locked write to memory space read from I/O space write to I/O space interrupt acknowledge indicate halt or indicate shutdown Non-pipelined Read Cycle Timing Non-pipelined Write Cycle Timing Pipelined Read- and Write-cycle timing READ and WRITE Bus Cycle Timing

24. M/IO D/C W/R Type of Bus Cycle Interrupt Acknowledge 0 0 0 0 0 1 Idle I/O data read 0 1 0 0 1 1 I/O data write 1 0 0 Memory code read 1 0 1 Halt/shutdown 1 0 1 Memory data read 1 1 1 Memory data write Non-pipelined Read Cycle Timing

25. Lect 09: Memory and I/O Interface and Memory Devices

26. Memory interface block diagram

27. Memory Subsystem Design Read-only Memory Random access read/write memories FLASH memory Wait-state Circuitry Cache memory Cache controller Read-Only Memory ROM, PROM, EPROM ROM BIOS(Basic Input/Output System) Read Operation : See Fig 10.4 Standard EPROM ICs : See Fig 10.6, 10.7, 10.9 Memory Devices and Subsystem Design

28. Random Access Read/Write Memories Static and Dynamic RAMs SRAM DRAM : refreshing Static RAM Block Diagram and Standard SRAM ICs : See Fig 10.11, 10.12, 10.13, 10.16 Read/Write Operation : See Fig 10.17, 10.18 RAM

29. Dynamic RAM Standard DRAM ICs : See Fig 10.19, 10.20, 10.21 Block Diagram of DRAM : See Fig 10.21, 10.22 Read/Write Operation Dynamic RAM

30. Read/Write-Cycle Timing

31. Lect 10: Memory Devices and Subsystem

32. FLASH memory array architecture

33. DRAM Example) 64K x 4 DRAM High Performance, CMOS silicon gate process 512-cycle refresh in 8 ms Optional FAST PAGE MODE access cycle Memory Modules

34. Memory Module

35. New DRAM Types SDRAM(Synchronous DRAM), EDO(Extended data-out DRAM), RAMBUS DRAM, SyncLink DRAM, ... Bandwidth (Scaling) is the issue Clock rate scaling Data transfer Bus width Synchronous DRAM Differences Synchronized Operation(CLK input) Multiple Bank Architecture Example) 2x2Mx4 Bits MB81117422E - 125/-100/-84/-67 Advanced DRAM Architectures