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Frame-Level Pipelined Motion Estimation Array Processor

Frame-Level Pipelined Motion Estimation Array Processor

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Frame-Level Pipelined Motion Estimation Array Processor

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  1. Frame-Level Pipelined Motion Estimation Array Processor Surin Kittitornkun and Yu Hen Hu IEEE Trans. on, for Video Tech., Vol. 11, NO.2 FEB, 2001

  2. OUTLINE • Methodology for VLSI Array Processors Design • An Example on Frame Level Block Matching Algorithm

  3. Design Levels • Sequential Algorithm • 1.DG Design • 2.SFG Design • 3.VLSI Array Design

  4. Dependence Graph (DG)

  5. DG: 1.Shift Invariant Shift-Unvariant DG for Sorting Algorithm Forifrom 1 to N Forjfrom 1 to i m(i+1,j) <- max[x(i,j), m(i,j)] x(i,j+1) <- min[x(i,j),m(i,j)]

  6. DG: 2.Localization Broadcast vs. Transmittent Data

  7. DG: 3.Reversible Arcs for Associative Operations • If the operation used in the recursion is associative, then the directions of the arcs may be reversible.

  8. DG: 4.Localization with Intermediate Variables Involved • AR Filtering Algorithm

  9. DG: 4.Localization with Intermediate Variables Involved • AR Filtering Algorithm • Spiral Communication Approach • Local Communication Approach

  10. Signal Flow Graph (SFG) Input(1) Output(1) x(n) x(n-1) D Input(2) Output(2)

  11. SFG Projection Procedure • For any projection direction, a processor space is orthogonal to the projection direction. • Replace the arcs in the DG with zero or nonzero delay edges between their corresponding processors. • Attach the input and output data to their corresponding processors.

  12. Projection Example Insertion sorting Insertion Sorting Selection Sorting Insertion Sorting Selection sorting Bubble sorting

  13. SFG to Systolic Array • Replace Operation Node with PE. • Place data and Input/Output pin with delay units.

  14. Frame-Level Pipelined Motion Estimation Array Processor Surin Kittitornkun and Yu Hen Hu IEEE Trans. on, for Video Tech., Vol. 11, NO.2 FEB, 2001

  15. Six-level nested Do-loop FSBM

  16. Two-level nested Do-loop FSBM

  17. Two-level nested Do-loop FSBM

  18. kth-clock cycle kth-clock cycle (v-1)NhN2 (h-1)N2 (i-1)N j

  19. 2D Localized DG of row 1, v=1 2p+1 2p+1 Search area and current frame coordinates of Nv = 3; Nh = 2; p =N/2 = 1.

  20. Linear SFG of (2p + 1)2 PEs, p = N/2 = 1 after systolic mapping of 2-D DG.

  21. Linear SFG of (2p + 1)2 PEs, p = N/2 = 1 after systolic mapping of 2-D DG.

  22. Systolic array with spiral interconnections

  23. Microarchitecture of PE

  24. Scheduled search area data

  25. Scheduled search area data

  26. Performance