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32-bit Pipelined RISC Processor PowerPoint Presentation
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32-bit Pipelined RISC Processor

32-bit Pipelined RISC Processor

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32-bit Pipelined RISC Processor

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  1. 32-bit Pipelined RISC Processor Group 1 aka “Go Us” CS m152b TA: Young Cho Lab section 1 Alice Wang Ann Ho Jason Fong

  2. IF/ID ID/EX EX/MEM MEM/WB Register File PC Control ALU Data Memory Instruction Memory General Review of a Pipelined Processor

  3. ? Two 16-bit words Data Memory 32-bit word One request 16-bit interface Request 32-bits Processor Memory 16-bits 16-bits Memory Controller Design 32-bit Design challenge: 32-bit processor with 16-bit memory interface On every memory access, need to get two words from memory Solution: Clock memory controller twice as fast as rest of processor Results in a memory access on the rising and falling edge of the processor’s clock cycle 32-bit

  4. funct shamt rt opcode opcode rd opcode rs rs opcode rd rt rs rs opcode rt opcode rt shamt funct 24 22 21 19 27 25 24 22 27 25 31 28 21 19 31 28 31 28 31 28 31 28 27 25 31 28 24 22 24 22 27 25 8 4 3 0 8 4 3 0 imm16 imm16 imm16 imm16 15 0 15 0 15 0 15 0 Instruction Format General instruction format 3 bits varies according to instruction type R-type instruction unused unused I-type instruction unused unused J-type instruction unused unused

  5. R-type instructions J-type instructions I-type instructions

  6. Our_mult Our Arithmetic Logical Unit

  7. Multiplier Uses a series of shifts and additions 0 0 0 0 0 0 0 0 0 0 0 Example: 13 x 11 = 01101 x 01011 LO HI 01101 01101 x = 01101 = 01101 + + = 1 1 0 1 0 1 1 0 1 1 multiplicand 01011 1 1 multiplier    = 143 0 0 1 0 0 0 1 1 1 1

  8. multiplier(more efficient, but more hardware)

  9. Forward From ALU output Forward From memory output ID/EX EX/MEM MEM/WB Data Forwarding

  10. PC Adder 1 Hold PC value Insert NOP NOP IF/ID Hardware NOP Insertion

  11. Data Forwarding and Stall Insertions:Observed Results Sample program: Bubble-sort 6 numbers Assembler insertion of NOPs Machine code size: 66 words of memory Execution time: ~750 clock cycles Hardware data forwarding and NOP insertion: Machine code size: 35 words of memory Execution time: ~400 clock cycles

  12. Data Forwarding and Stall Insertions:Observed Results • Savings in memory and execution time • Much simpler assembler • But hardware is now more complex • Tradeoff between hardware complexity and software complexity • Also demonstrates benefits of understanding the underlying architecture when designing an assembler

  13. Conclusion • Some problems we encountered: • Off by one stage in pipeline • Lack of experience with VHDL • Order of bits from memory • In Conclusion... • Knowledge from previous courses • Further research • Simple RISC processor • Pipelining • Multiplier • Data Forwarding and Hardware NOP’s ENEMIES OF THE HEIR, BEWARE

  14. References • Hennessey and Patterson, Computer Organization and Design (2nd Ed.), 1998, pages 476-495 • Donaldson, John L., “Pipeline Hazards”, • http://occs.cs.oberlin.edu/faculty/jdonalds/317/lecture08.html • Ercegovac, Intro To Digital Systems • Add more references from lab 4