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Pipelined Processor Design. Instruction execution decomposed into Five stages: IF : Instruction Fetch ID : Instruction Decode ALU : ALU operation MEM : Data memory Read or Write WB : Writeback to register Successive stages of the pipeline separated by Pipeline Registers

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pipelined processor design
Pipelined Processor Design

Instruction execution decomposed into

Five stages:

IF: Instruction Fetch

ID: Instruction Decode

ALU: ALU operation

MEM: Data memory Read or Write

WB: Writeback to register

  • Successive stages of the pipeline separated by Pipeline Registers
  • Each stage takes 1 clock cycle
  • Inputs to a stage are
    • Read from the pipeline register on the left
    • Results clocked into pipeline register on the right at end of clock cycle
execution of lw instruction lw rt d rs
Execution of lw Instruction: lw Rt, d(Rs)

IF ID EX MEM WB

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PC

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5 stage processor pipeline

P

C

P

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P

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5-Stage Processor Pipeline

T=1

T=2

T=3

T=4

T=5

IF

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EX

MEM

WB

IF

ID

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WB

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5 stage processor pipeline1

P

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5-Stage Processor Pipeline

T=1

T=2

T=3

T=4

T=5

IF

ID

EX

MEM

WB

P

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IF

ID

EX

MEM

WB

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IF

ID

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performance measures
Performance Measures
  • Instruction Latency Time elapsed between start and finish of the instruction
    • 5 clock cycles
  • CPI: Average number of cycles per instruction
    • n instructions in an ideal p-stage pipeline require n+p-1 cycles
    • CPI = n+p-1/n = 1 + p-1/n
    • Isolated instruction (n=1): p cycles
    • Large n: CPI tends to 1
  • IPC : (cycles/instruction)
    • Number of instructions completed per cycle: 1/CPI : 1/ 1 + (p-1)/n
    • Tends to 1 instruction/cycle for ideal pipeline
  • Instruction Throughput (instruction/sec)
    • Number of instructions completed per second:

IPC x Cycles/second = IPC x Clock Frequency

pipeline hazards
Pipeline Hazards
  • Hazard
    • Condition that disrupts the orderly flow of instructions
    • Requires special attention by hardware and/or software to maintain program correctness and performance
    • Structural Hazards

Contention for hardware resources

    • Data Hazards

Data dependencies between instructions

    • Control Hazards

Disruptions caused by program control flow

structural hazards
Structural Hazards

Contention for hardware resources

Memory, Register File, ALU

Example:

Suppose instruction and datamemory were combined

A: LD R1, 1000(R2)

B: ADD R3, R4, R5

C: ADD R6, R7, R8

D: ADD R9, R10, R11

memory contention hazard

A

F

E

B

C

Memory Contention Hazard

IF

ID

EX

MEM

WB

T=1

T=2

T=3

T=4

T=5

T=6

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IF

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WB

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IF

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IF

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IF

ID

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MEM

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IF

ID

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WB

memory contention hazard1

A

F

E

B

C

Memory Contention Hazard

IF

ID

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MEM

WB

T=1

T=2

T=3

T=4

T=5

T=6

A

IF

ID

EX

MEM

WB

B

A

IF

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MEM

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memory contention hazard2
Memory Contention Hazard

Time ABCDEF

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  • Instructions A and Dcontend for memory at cycle 4
      • Every instruction reads instructions from memory at cycle 1
      • LD and SD instructions write to memory at cycle 4
  • Solution
  • Separate instruction and data memories
structural hazards1
Structural Hazards
  • Structural Hazards
    • Contention for hardware resources
      • Memory
        • Is 1 cycle access for memory realistic?
      • Register File
structural hazard register contention

A

F

E

B

C

Structural Hazard: Register Contention

IF

ID

EX

MEM

WB

T=1

T=2

T=3

T=4

T=5

T=6

A

IF

ID

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MEM

WB

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IF

ID

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D

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structural hazard register contention1

A

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Structural Hazard: Register Contention

IF

ID

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MEM

WB

T=1

T=2

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T=4

T=5

T=6

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register contention hazard
Register Contention Hazard

Time ABCDEF

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  • Instructions A and Dcontend for register file at cycle 5
      • All instructions (except Store, Branch) write to Register File incycle 5
      • All instructions (except jump) read Register File in cycle 2
  • Solution:
  • :Multi-ported register file: Design register file to allow concurrent accesses
          • 2 Read ports and 1 Write port
          • Write in first half of cycle, reads in second half
          • Read returns the value written in first half cycle
pipeline hazards1
Pipeline Hazards
  • Hazard

Condition that disrupts the orderly flow of instructions

Requires special attention by hardware and/or software to maintain program correctness and performance

    • Structural Hazards

Contention for hardware resources

    • Data Hazards

Data dependencies between instructions

    • Control Hazards

Disruptions caused by program control flow

data dependencies
Data Dependencies

Dependent instructions: access common storage location

  • I1 and I2 instructions that access a common storage location
    • Read-after-Read (RAR) dependency
      • I2 reads the location read by I1

I1: ADD R1, R2, R3

I2 : ADD R4, R5, R2

      • Both I1 and I2 read register R2
    • Read-after-Write (RAW) dependency
      • I2 reads the location written by I1
      • No instruction between I1 and I2 writes to the same location

I1: ADD R1, R2, R3

I2: ADD R4, R1, R2

      • I2 reads the value in register R1 that was written by I1
data dependencies1
Data Dependencies
  • I1 and I2 instructions that access a common storage location
    • Write-after-Read (WAR) dependency:
      • I2 writes the location read by I1

I1: ADD R1, R2, R3

I2: ADD R2, R4, R5

      • I1 must read value of R2 prior to write by I2
    • Write-after-Write (WAW) dependency:
      • I2 writes the location written by I1

I1: ADD R1, R2, R3

I2: ADD R1, R4, R5

      • Write of R1 by I1 must not occur after the write by I2
      • Final value of R1 due to write by I2 and not I1
when is a dependency a hazard

A

B

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IF

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IF

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When is a dependency a hazard?

WAR Hazard

A : ADD R1, R2, R3

B : ADD R2, R4, R5

Register readsoccur at anearlier pipeline stage than write

  • A reads R2 at cycle 2.
  • B writes R2 at cycle 6 (or later)
  • No WAR hazards in this pipelined implementation
when is a dependency a hazard1

A

B

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IF

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When is a dependency a hazard?

WAW Hazard

A : ADD R1, R2, R3

B : ADD R1, R4, R5

  • Register writes occur only in WB stage
    • A writes R1 at cycle 5.
    • B writes R1 at cycle 6 (or later)
  • No WAW hazards in pipelined implementation
when is a dependency a hazard2
When is a dependency a hazard?

RAWHazard

A : ADD R1, R2, R3

B : ADD R4, R1, R5

  • Hazard possible since register reads occur earlier than writes
    • A writes R1 at cycle 5
    • B may read R1 at cycle 3, 4 or 5

Example: A and B consecutive instructions

A

B

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  • Instruction B reads stale value in R1 beforeit is updated byA (HAZARD!!)
raw hazards

IF

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RAW Hazards

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  • A and B separated by 1 instruction: Hazard

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WB

A

  • A, B separated by 2 instructions
  • Hazard depends on register file design
  • No Hazard with split read/write protocol with writes earlier in cycle
raw hazards1

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RAW Hazards

IF

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A, B separated by 3 instructions: No Hazard

  • Register file design alternatives:
    • value returned by read equals the value being written at that cycle
    • value returned by read is the old value
    • 1 implies no RAW hazard
    • 2 implies RAWhazard
pipeline hazards2
Pipeline Hazards
  • Hazard

Condition that disrupts the orderly flow of instructions

Requires special attention by hardware and/or software to maintain program correctness and performance

    • Structural Hazards

Contention for hardware resources

    • Data Hazards

Data dependencies between instructions

    • Control Hazards

Disruptions caused by program control flow

lazy execution of branch equal instruction beq rt rs d
Lazy Execution of Branch Equal Instruction: beq Rt, Rs, d

IF ID EX MEM WB

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<<

talking points
Talking Points

Additional Discussion points in Lecture:

1. Cache needed for single--cycle access

What happens on a miss?

Simple calculation to show increase in CPI:

100% instruction cache hits

95% Data cache hit

20% Load/Store instructions

Miss Penalty 100 cycles

Total stall cycles (per instruction): 20/100 x 5/100 x 100 = 1.0 cycle

CPI = 1.0 + 1.0 = 2.0

2. MIPS = 10^6 x CPI x Frequency (Hz)

Clock frequency determined by the delay through the pipeline stage

faster circuitry

less circuitry

Deep pipelines with very thin stages: can increase the clock rate at the expense of latency

Instruction throughput increases