html5-img
1 / 39

8-bit Timer/Counter0

8-bit Timer/Counter0. (with PWM and Asynchronous Operation). Main Features. Single Channel Counter Clear Timer on Compare Match (Auto Reload) Phase Correct Pulse Width Modulator (PWM) Frequency Generator 10-bit Clock Prescaler Overflow and Compare Match Interrupt Source (TOV0 and OCF0)

alton
Download Presentation

8-bit Timer/Counter0

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. 8-bit Timer/Counter0 (with PWM and Asynchronous Operation)

  2. Main Features • Single Channel Counter • Clear Timer on Compare Match (Auto Reload) • Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • 10-bit Clock Prescaler • Overflow and Compare Match Interrupt Source (TOV0 and OCF0) • Allow Clocking from External

  3. Registers • Timer/Counter Control Register (TCCR0) : contains bits to control the operations of Timer/Counter • Timer/Counter Register (TCNT0) : holds the value that the counter counts • Output Compare Register (OCR0) : contains an 8-bit value that is continuously compared with TCNT0 value to determine if the counting reaches its TOP value • Timer Interrupt Flag Register (TIFR) : contains interrupt flag bits for various Timer/Counters • Timer Interrupt Mask Register (TIMSK) : contains interrupt mask bits to mask individual interrupts

  4. Counter Unit • Main part of the 8-bit Timer/Counter

  5. Counter Unit (cont’d) • Internal signals : • count : increment or decrement TCNT0 by 1 • direction : select between increment and decrement • clear : clear TCNT0 (set all bits to 0) • clkTN : Timer/Counter clock (default = clkI/O) • TOP : signalizes that TCNT0 has reached MAX(0xFF) value or the value stored in OCR0 reg. • BOTTOM : signalizes that TCNT0 has reached the bottom when it becomes zero (0x00)

  6. Output Compare Unit • Compares continuously TCNT0 with OCR0. Whenever TCNT0 = OCR0, this unit signals a match set Output Compare Flag (OCF0)  (if OCIE0 is enabled) generates an output compare interrupt

  7. Waveform generator • Waveform generator uses the match signal to generate an output according to operating mode set by the WGM01:0 bits and compare output mode (COM01:0) bits. The MAX and BOTTOM signals are used by the waveform generator for handling the special cases of the extreme values in some modes of operation

  8. Mode of operations : defined by the combination of WGM01:0 and COM01:0 bits in TCCR register • Normal mode : Counting direction is always up (incrementing), and no counter clear is performed. When the counter reaches its max 8-bit value (TOP = 0xFF), it restarts from the bottom (0x00) and Timer/Counter overflow flag (TOV0) is set. • Clear Timer on Compare Match (CTC) mode : thecounter value (TCNT0) increases until a compare match occurs between TCNT0 and OCR0. If the match occurs, the counter (TCNT0) is cleared and an interrupt request signal is generated at each match (the counter value reaches the TOP value).

  9. Waveform freq. = fclk_I/O / 2*N*(1+OCRn)N : prescaler factor (1,8,32,64,128,256, or 1024)

  10. Changing the TOP to a value close to BOTTOM when the counter is running must be done with care : If a new value written to OCR0 is lower than the current value of TCNT0, the counter will miss the compare match  The counter will have to count its maximum value (0xFF) and wrap around starting at 0x00 before the compare match can occur

  11. For generating a waveform output in CTC mode, the OC0 output can be set to ‘toggle’ its logic level on each compare match by setting the Compare Output mode bits to Toggle mode (COM01:0). • The OC0 value will not be visible on the port pin unless the data direction for the pin is set to output. • Waveform freq. = fclk_I/O / 2*N*(1+OCRn)N : prescaler factor (1,8,32,64,128,256, or 1024) • When OCRn = 0x00, the waveform with a maximum frequency is generated : (fclk_I/O / 2)

  12. Timer/Counter Prescaler • Prescaler receives system clock (fCLK_I/O) and generates the prescaled clocks that have frequencies of fCLK_I/O/8, fCLK_I/O/32, fCLK_I/O/64, fCLK_I/O/128, fCLK_I/O/256, or fCLK_I/O/1024 --- the scale factor is selected by CS02:0 bits in TCCR0 (p.101~103)

  13. Timer/Counter Prescaler Block Diagram

  14. Fast PWM Mode • Provides a high frequency PWM waveform generation option. • Single-slope operation : the counter counts from BOTTOM to MAX, then restarts from BOTTOM • Non-inverting Compare Output mode(COM01:0 bits = 10) : OC0 is cleared on the compare match, and set at BOTTOM • Inverting Compare Output mode(COM01:0 bits = 11) : OC0 is set on the compare match, and cleared at BOTTOM

  15. PWM frequency = fclk_I/O / N*256N : prescaler factor (1,8,32,64,128,256, or 1024) • If OCR0 = BOTTOM, the output will be a narrow spike If OCR0 = MAX, the output will be constantly high or low

  16. Phase Correct PWM Mode • Dual-slope operation : the counter counts repeatedly from BOTTOM to MAX (upcounting), then from MAX to BOTTOM (downcounting). • In non-inverting mode, OC0 is cleared on the compare match between TCNT0 and OCR0 while counting up, and set on the compare match while downcounting. • In inverting mode, the operation is inverted. • Output Compare (Ocn) Interrupt Flag is set each time the compare match occurs. • Timer Overflow (TOV0) Interrupt Flag is set each time the counter reaches BOTTOM. • Symmetric feature  preferred for motor control applications.

  17. PWM frequency for the output when using phase correct PWM :fOCnPCPWM = fclk_I/O /N*510N : prescaler factor (1,8,32,64,128,256, or 1024)

  18. Timer/Counter Timing Diagram

  19. Timer/Counter Control Register(TCCR0) • Bit 7 - FOC0 (Force Output Compare) : When FOC0 = 1, an immediate compare match is forced on the waveform generation unit • Bit 6,3 – WGM01:0 (Waveform Generation Mode) : controls the counting sequence of the counter, the source for the max (TOP) counter value, and type of waveform generation

  20. (CTC Mode) • Bit 5:4 – COM01:0 (Compare Match Output Mode) : control the output compare pin (OC0) behavior

  21. Bit 2:0 – CS2:0 (Clock Select)

  22. Timer/Counter Register (TCNT0) • Allows direct access (read/write) to Timer/Counter unit 8-bit counter

  23. Output Compare Register (OCR0) • Contains an 8-bit value that is continuously compare with the counter value (TCNT0). A match can be used to generate an output compare interrupt, or to generate a waveform output on the OC0 pin

  24. Timer/Counter Interrupt Mask Register (TIMSK) • Bit 1 (OCIE0) : Timer/Counter0 Output Compare Match Interrupt Enable • Bit 0 (TOIE0) : Timer/Counter0 Output Overflow Interrupt Enable

  25. Timer/Counter Interrupt Flag Register (TIFR) • Bit 1 (OCEF) : Output Compare Flag 0, is set when a compare match occurs between TCNT0 and the data in OCR0 • Bit 0 (TOV0) : Timer/Counter0 Overflow Flag

  26. Asynchronous operation • The mode that Timer/Counter is not clocked from the I/O clock (clkI/O) but clocked from the external clock • Asynchronous Status Register (ASSR) • If AS0 bit = 0, T/C is clocked from the I/O clock (clkI/O). If AS0 bit = 1, T/C is clocked from a low-frequency (watch) crystal Oscillator (32.768 KHz: refer to p.37) connected to the Timer Oscillator 1 (TOSC1) pin

  27. TCN0UB (Timer/Counter0 Update Busy) : a logical 0 in this bit indicates that TCNT0 is ready to be updated with a new value. • OCR0UB (OCR0 Update Busy) : a logical 0 in this bit indicates that OCR0 is ready to be updated with a new value. • TCR0UB (TCCR0 Update Busy) : a logical 0 in this bit indicates that TCCR0 is ready to be updated with a new value. * If write a value into any of the registers when the Busy flag is set to 1, the updated value may be corrupted

  28. .include "C:\Program Files\Atmel\AVR Studio\Appnotes\m128def.inc" • ; • .ORG $0000 • RJMP RESET • .ORG OVF0addr • RJMP TIMER_OV • .def TEMP = R16 • .def TIME = R17 • .def CLK_SRC = R18 • RESET: • LDI TEMP, LOW(RAMEND) ; Initialization of Stack Pointer • OUT SPL, TEMP • LDI TEMP, HIGH(RAMEND) • OUT SPH, TEMP • LDI CLK_SRC, $04 ; Setup clock source as TOSC1 input • OUT ASSR, CLK_SRC ; (32.768KHz) • LDI TIME, $FC ; Setup TCNT0 with the Initial value($FC) • OUT TCNT0, TIME ; TCNT0 <- 11111100 • LDI TEMP, (1<<TOIE0) ; Timer overflow interrupt enable • OUT TIMSK, TEMP

  29. LDI TEMP, $05 ; Set the operation mode to Normal mode and OUT TCCR0, TEMP ; the clock prescaler to CLK/128 • ;  32.768 KHz / 128 = 256 Hz • ;  TOV Interrupt occurs every 1/64 sec • SEI • LDI TEMP, 0xFF • OUT DDRB, TEMP ; Set all pins of Port B to output mode • LDI TEMP, 0x55 • LOOP: OUT PORTB, TEMP ; Wait in the loop with writing the value TEMP • ; to Port B • RJMP LOOP • TIMER_OV: ; Timer Overflow Interrupt Service Routine • CLI • OUT TCNT0, TIME ; Re-setup the initial count value • DEC TEMP ; Change the value written to the Port B • SEI • RETI

More Related