8-bit X 8-bit SRAM and 3 X 8 Decoder Irina Vazir, Prabhjot Balaggan and Sumandeep Kaur Advisor: Dr. David Parent December 06, 2004
Agenda • Abstract • Introduction • Project Details • Results • Cost Analysis • Conclusions
Abstract • We designed an 8-bit X 8-bit SRAM and a 3 X 8 decoder that operated at 200 MHz and uses 5.425 mW of Power and occupied an area of 462 mm x 532 mm.
Introduction • SRAM: Memory circuit that permits writing and reading, stored data can be retained indefinitely without any periodic refresh. • 1-bit data storage cell: Full CMOS SRAM cell configuration. • Equation used for wn and wp of the cell: (W/L)3/ (W/L) 1 < 2(VDD – 1.5VT,n)1.5VT,n (VDD – 2VT,n)2
Project Details • 8-bit X 8-bit SRAM that operates at 5ns. • The project was divided into subsystems namely the SRAM cell, precharge circuit, sense amplifiers, write circuit, mux-based DFF’s and the decoder. • Output of the decoder specifies address for the SRAM cells, where the data needs to be written or read from.
Longest Path Calculations for the Decoder Note: All widths are in microns and capacitances in fF
Cost Analysis Task Number of days • Verifying Logic: 4 days • Verifying Timing: 7 days • Layout: 8 days • Post Extracted Timing: 1 day
Lessons Learned • Start early. • Test at every phase. • No IT support on weekends. • Planning is very important.
Summary • We designed an 8-bit X 8-bit SRAM and a 3 X 8 decoder that operated at 200 MHz and uses 5.425 mW of Power and occupied an area of 462 mm x 532 mm. • Future designs can definitely minimize area.
Acknowledgements • Thanks to our family members for putting up with us. • Thanks to Cadence Design Systems for the VLSI lab. • Thanks to Synopsys for Software donation. • Thanks to Professor Parent for his guidance throughout the project.