hybrid conditional sum carry lookahead adder l.
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Hybrid Conditional Sum/Carry Lookahead Adder. by Stephen Malchi. Project objective. To design a low power high performance adder Sub micron technology Power is the main concern. Conditional Sum Adder. Generates individual sum and carry bits.

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Presentation Transcript
project objective
Project objective
  • To design a low power high performance adder
  • Sub micron technology
  • Power is the main concern
conditional sum adder
Conditional Sum Adder
  • Generates individual sum and carry bits.
  • Selects the true output based on the carry of previous stage.
theoretical delay
Theoretical Delay
  • Conditional Sum Adder

T = (log2n +1).2∆ = 18∆

  • Hybrid Adder

producing g’s and p’s 1∆

producing internal carries 2∆

3 ∆ * 4 = 12 ∆

design
Design
  • Verilog gate level simulated and verified for functionality using Modelsim.
design styles
Static CMOS

CPL (Complementary Pass Transistor Logic)

Most efficient pass transistor logic

Small input load and good output driving capability

Reto Zimmermann and wolfgang Fichtner, Low- Power Logic Styles: CMOS versus Pass-Transistor Logic

Design Styles
simulation result

Adder

Adder

Power (mW)

Power (mW)

Delay (ps)

Delay (ns)

CSA

CSA

2.80

6.34

714

1.2

HCSA

HCSA

1.65

5.65

0.676

349

CCA

CCA

1.78

5.25

648

1.02

HCCA

HCCA

1.56

4.83

0.632

348

Simulation Result

Static CPL

conclusion
Conclusion
  • Hybrid Adder performance is better
  • The advantages of CPL are restricted by the swing restoration circuitry
  • Static is a better choice than CPL.
  • Conditional Carry adder
  • Reduces the MUX count by half in turn saves power and increases speed.
references
References
  • [1] Behrooz Parhami – Computer Arithmetic Algorithms and Hardware Designs.
  • [2] Kuo-Hsing Cheng, Shu-Min Chiang and Shun –Wen Cheng – The Improvement of Conditional Sum Adder for Lower Power Applications.
  • [3] J.Slansky, Conditional Sum Addition logic. IRE Trans. Electron Computer. VOL EC-9 (1960).
references cont
References cont.
  • [4] Reto Zimmermann and wolfgang Fichtner, Low- Power Logic Styles: CMOS versus Pass-Transistor Logic.