Hybrid Conditional Sum/Carry Lookahead Adder. by Stephen Malchi. Project objective. To design a low power high performance adder Sub micron technology Power is the main concern. Conditional Sum Adder. Generates individual sum and carry bits.
Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.
T = (log2n +1).2∆ = 18∆
producing g’s and p’s 1∆
producing internal carries 2∆
3 ∆ * 4 = 12 ∆
CPL (Complementary Pass Transistor Logic)
Most efficient pass transistor logic
Small input load and good output driving capability
Reto Zimmermann and wolfgang Fichtner, Low- Power Logic Styles: CMOS versus Pass-Transistor LogicDesign Styles