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Device Considerations for Low Power VLSI Circuits

Device Considerations for Low Power VLSI Circuits. EDS Silicon Valley Chapter David Kidd Senior Director of Digital Design. Overview. T ransistor Variability Limits Chips Impact on Mobile System on Chip (SOC) Limited Low Power Design Techniques Where does Variability come from?

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Device Considerations for Low Power VLSI Circuits

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  1. Device Considerations for Low Power VLSI Circuits EDS Silicon Valley Chapter David Kidd Senior Director of Digital Design

  2. Overview • Transistor Variability Limits Chips • Impact on Mobile System on Chip (SOC) • Limited Low Power Design Techniques • Where does Variability come from? • New Transistor Alternatives to Reduce Variability • Deeply Depleted Channel (DDC) technology • Silicon Impact • Outlook • Taking advantage of Deeply Depleted Channel (DDC) technology in Mobile SOC

  3. What is needed in Mobile System on Chip? MC (LPDDR) Flash CPU (1.5GHz) GPU (500MHz) BT WiFi GPS 3GLTE RF High Frequency • Multiple blocks with different performance requirements • Integrated on the same die • Different power modes – would like to run at different supplies • Multiple VT transistors used to control leakage • Single chip solution requires analog integration • Need co-design of architecture, circuits and transistor technology for best solution Medium Frequency L2 (1MB) Lower Frequency Crypto, Security HD Video, H264, MPEG PMU Memory

  4. Variability Limits Design & Architecture • Limited benefit using voltage scaling (DVFS) • Cannot overdrive much due to reliability and power restrictions • Dynamically lowering voltage limited to 100-200mV • Only lowering frequency leaves large leakage power • “Run to hold” beats DVFS despite overhead • Finicky SRAM memories • High SRAM VMIN leaves no room for memory voltage scaling • Many circuit tricks to improve VMIN and noise margins • Design teams moved to dedicated power rail for SRAM • Works for CPU – difficult in GPU • Impacts power network integrity – more fluctuations • Transistor variability limits chips

  5. Transistor Variation Source of Chip Variation • Global/Systematic/Manufacturing Variation • Shifts all the transistors similarly • Longer/shorter transistor lengths • More (or less) implant energy and dose • Will result in speed/power distribution • Local/Random Variation • Transistor next to each other vary widely • Small number of dopants in transistor channel • Random Dopant Fluctuation (RDF) • Apparent in threshold voltage mismatch (σVT) • Impacts speed, leakage, SRAM & Analog • Industry solution: Remove RDF usingUndopedChannel • What is the right silicon roadmap going forward? Too slow Too hot UseableYield [#Transistors]

  6. Transistor Alternatives • FinFET or TriGate • Promises high drive current • Manufacturing, cost, and IP challenge • Doped channel to enable multi VT • FDSOI • Showing off undoped channel benefits • Good body effect, but lack of multi VT capability • Restricted supply chain • DDC – Deeply Depleted Channel transistor • Straight forward insertion into Bulk Planar CMOS • Undoped channel to reduce random variability • Good body effect and multi VT transistors Source: GSS, Chipworks Textbook FinFET Intel TriGate Source: IMEC Source: Fujitsu

  7. Deeply Depleted Channel™ (DDC) Transistor • Undoped or very lightly doped region • Significantly reduced transistor random variability sVT • Lower leakage • Better SRAM (IREAD, lower Vmin & Vret) • Tighter corners • Smaller area analog design • Higher channel mobility (increased Ieff, lower DIBL) • Higher speed, improved voltage scaling • VTsetting offset region • Enables multiple threshold voltages • Screening region • Strong body coefficient • Bias bodies to tighten manufacturing distribution • Body biasing to compensate for temperature and aging 1 1 2 2 3 3 *Example implementation Benefits similar to FinFET in planar bulk CMOS

  8. Bulk Planar Foundry-Compatible Process • No new materials / No new tools SuVolta Flow (example) Foundry Standard Flow Wells and VT STI Blanket Epi New Wells and VT STI Poly Poly Spacers and LDDs Spacers and LDDs Salicide Salicide Gate Gate Metal Layers Metal Layers

  9. TEM of DDC Transistor and STI Presented at IEDM 2011 D S 43.1nm

  10. Lower Transistor VariabilityReduces Leakage • Transistor variability is reflected in threshold voltage (VT) distribution • Leakage current is exponentially dependent on VT • Lower VT variability (sVT) reduces number of leaky low VT devices • Power dissipation is dominated by low VT edge of distribution • Smaller sVT Less leakage power for digital and memory/SRAM 65nm SiliconSRAM VT [#Transistors] High leakage tail dominates power [Leakage Power] 2.7x higher power (Model using 85mV subVT slope) High VT tail Slows down ICs High leakage tail

  11. Lower Transistor Variability Improves Speed • Nominal (TT) ring oscillator speed expected to be 400ps (A) • Equivalent to having many similar critical paths in a chip • VT variation will randomly affect paths within the same die limiting speed to 470ps • Undoped channel reduces variability and increases mobility (B) • 25% faster mean, 30% faster tail due to tighter distribution • To match performance lower VDD until tails have same speed (C) • Large impact on power due square dependence P=CV2f +IV 65nm Silicon Measurement (B) (A) (C)

  12. Sub 0.5V VMin is Possible • SRAM memories built using 6-T SRAM cell • Smallest transistors on every chip, worst VT mismatch • Higher VDD is required to avoid failures • SRAM blocks limit VDD scaling • Vmin – lowest operating voltage limited by transistor mismatch • Demonstrated SRAM to Vmin of 0.425V • Standard SRAM macros • No circuit “tricks” for low voltage operation • Demonstrates potential for 50% voltage scaling DDC 300 mV Industry Norm Tester limit

  13. Baseline DDC Baseline DDC Baseline DDC Baseline DDC Improved VT Matching Key for Low VMIN • 40-60% improved matching for SRAM transistors Presented at IEDM 2011

  14. Design Examples Analog • In analog circuits, matching is key • Large transistors used to improve relative variability in current mirrors, differential pairs, etc. • Better transistor matching allows for • Area savings • Higher performance • Lower power • Undoped channel improves ROUT higher gain • OpAmp stage • Matched bandwidth, gain, slewrate • Over 50% smaller area (84 vs 190μm2) • 45% better input noise (176 vs 327 μV) • Bandgap reference circuit • Same accuracy achieved at half the size Baseline DDC Baseline DDC 420um 210um 450um 450um 10.9x17.4um 6.9x12.2um SuVolta sample layout

  15. Better Chips with Body Biasing • Body Bias to fix systematic variation • Speed-up (forward bias - FBB) slow parts • Cool down (reverse bias - RBB) hot parts  Increase manufacturing yield • Body bias enables multiple modes of operation • Active  minimize power at every performance • Standby  leakage reduction, power gating • DDC transistor provides 2-4x larger body factor Too slow Too hot UseableYield FBB RBB TCAD prediction

  16. Half the Power at Matched Performance • Inverter ring-oscillators (RO) fabricated at process corners • Baseline @ 1.2V VDD and DDC @ 0.9V VDD • For each corner, DDC transistor RO is faster and lower power • Using strong body coefficient to pull in corners • Half the power (50% less power) while matching speed 65nm Silicon Measurement Baseline speed FF FF TT 100% power TT SS SS 50% power

  17. Tighter Manufacturing Corners w/ DDC • Better process control leads to tighter corners • Manufacturing flow further reduces layout effects • 1 sigma tighter wafer to wafer and within wafer variation for DDC • Less overdesign as max paths and min (hold) paths are closer • Faster design closure  earlier tapeout shorter TTM POR 3s 2s VDD=1.2V 1s VDD=0.9V 65nm Silicon Measurement

  18. Voltage Scaling to 0.6V VDD • Achieve half the speed at 1/6 the power @0.6V VDD • Use body bias to compensate for temperature and aging • Critical for low VDDoperation • Enable workable design window – avoid overdesign 65nm Silicon Measurement FF Baseline TT SS -83% DDC

  19. This is HotChips – Go Faster! • Turbo Mode: DDC transistor achieves over 50% speedup @ 1.2V VDD • All corners for DDC runat 580MHz vs 370MHz for baseline +56% 65nm Silicon Measurement

  20. 28nm and Beyond • Same performance at 0.75V VDD as baseline at 0.9V VDD • 30% lower power • Alternatively 25% faster at same voltage • Even better when using body bias to pull in corners • (silicon calibrated SPICE simulations)

  21. Applying DDC to Lower Variability in Mobile SOC MC (LPDDR) Flash CPU (1.5GHz) GPU (500MHz) BT WiFi GPS 3GLTE RF High Frequency • CPU: Single thread performance critical • Push frequency by temporarily raising voltage in turbo mode • DVFS with body biasing becomes DVBFS • GPU: High number of cores using small transistors • Less overdesign due to lower delay variability • Increase parallelism, lower voltage, body bias dynamically for more pixels/Watt • Lower frequency blocks • In addition to high VT transistors also run at lower voltage and optimal body bias • Whole chip: Use body bias to adjust for manufacturing variation • Take advantage of improved memory and analog performance • Lowering variability while compatible with existing bulk planar silicon IP Medium Frequency L2 (1MB) Lower Frequency Crypto, Security HD Video, H264, MPEG PMU Memory

  22. Conclusions • Variability limits chips • DDC transistor reduces random variability through its undoped channel • DDC transistor’s strong body factor can be used to fix systematic variation and compensate for temperature variation • DDC technology provides performance kicker from 90nm to 20nm • Straight forward integration into existing nodes • Compatible with existing bulk planar CMOS silicon IP • Use existing CAD flow • DDC technology brings back low power tools • Large range DVFS • Body biasing • Low voltage operation • Taking advantage of reduced variability DDC transistor in design and architecture will lead to next level in mobile SOC

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