Input-Specific Dynamic Power Optimization for VLSI Circuits

1. Input-Specific Dynamic Power Optimization for VLSI Circuits Fei Hu Intel Corp. Folsom, CA 95630, USA Vishwani D. Agrawal Department of ECE Auburn University, AL 36849, USA October 5, 2006

2. Outline • Background • Dynamic power dissipation • Glitch reduction • Previous LP model with fixed gate delay • Process-variation-resistant LP model • Input-specific optimization • Without process-variation • With process-variation • Experimental results • Conclusion Fei Hu, ISLPED 2006, Tegernsee, Germany

3. Background • Dynamic power dissipation • Pdyn= Pswitching + Pshort-circuit • Switching power dissipation • Pswitching = 1/2 kCLVdd2fclk Fei Hu, ISLPED 2006, Tegernsee, Germany

4. Background • Glitch reduction • A important dynamic power reduction technique • Glitch power consumes 30~70% Pdyn • Related techniques • Balanced delay • Hazard filtering • Transistor/Gate sizing • Linear Programming approach Fei Hu, ISLPED 2006, Tegernsee, Germany

5. Glitch reduction • Original circuit • Balanced path/ path balancing • Equalize delays of all path incident on a gate • Balancing requires insertion of delay buffers. • Hazard/glitch filtering • Utilize glitch filtering effect of gate • Not necessary to insert buffer Fei Hu, ISLPED 2006, Tegernsee, Germany

6. Glitch reduction • Transistor/gate sizing • Find transistor sizes in the circuit to realize the delay • No need to insert delay buffers • Suffers from nonlinearity of delay model • large solution space, numerical convergence and global optimization not guaranteed • Linear programming approach • Adopts both path balancing and hazard filtering • Finds the optimal delay assignments for gates • Uses technology mapping to map the gate delay assignments to transistor/gate dimensions • Guarantees optimal solution, a convenient way to solve a large scale optimization problem Fei Hu, ISLPED 2006, Tegernsee, Germany

7. Previous LP approach Circuit delay constraints: T11 ≤ maxdelay T12 ≤ maxdelay Objective: Minimize sum of buffer delays Timing window (t, T) Gate constraints: T7 T5 + d7 T7 T6 + d7 t7≤ t5 + d7 t7≤ t6 + d7 d7> T7 – t7 t6 T6 t7 T7 d7 t5 T5 Fei Hu, ISLPED 2006, Tegernsee, Germany

8. Process-variation-resistant optimization • Motivation • Gate delay assumed fixed in previous models • Variation of gate delay in real circuits • Environmental factors: temperature, Vdd • Physical factors: process variations • Effect of delay variation • Glitch filtering conditions corrupted • Power dissipation increases from the optimized value • Our proposal • Consider delay variations in dynamic power optimization • Only consider process variations (major source of delay variation) Fei Hu, ISLPED 2006, Tegernsee, Germany

9. LP model based on statistical timing • Statistical timing model with random variables Fei Hu, ISLPED 2006, Tegernsee, Germany

10. Outline • Background • Dynamic power dissipation • Glitch reduction • Previous LP model with fixed gate delay • Process-variation-resistant LP model • Input-specific optimization • Without process-variation • With process-variation • Experimental results • Conclusion Fei Hu, ISLPED 2006, Tegernsee, Germany

11. Input-specific optimization • Motivation • Previous LP models guarantee glitch filtering for ANY input vector sequence • Ti - ti < di for all gates • Redundancy in optimization • Insertion of more buffers • Increased overhead in power/area • In reality, gates are under embedded environments • Optimization for input vector sequence that is possible for the circuit, e.g., functional vectors • Same reduction in power dissipation with lower overheads Fei Hu, ISLPED 2006, Tegernsee, Germany

12. Input-specific optimization • Glitch generation pattern • Input vector pair that can potentially generate a glitch • AND gate example: • Glitch generation probability Pg[ i ] = Ng[ i ] / N • Probability glitch-generation pattern occurs at inputs of gate i • Steady state signal values match the pattern Fei Hu, ISLPED 2006, Tegernsee, Germany

13. Input-specific optimization • Application to basic LP model w/ fixed gate delay model • Static optimization • Only static glitches/hazards considered • Relaxation of constraints • Relax glitch filtering constraints where glitches unlikely • Ti - ti < di=> (Ti – ti)*i < di • Selective relaxation • Generalized relaxation Fei Hu, ISLPED 2006, Tegernsee, Germany

14. Input-specific optimization • Application to process-variation-resistant LP model based on statistical timing • Static optimization • Relaxation of constraints • Selective relaxation • Generalized relaxation • Tuning factor • Original objective • Current objective Fei Hu, ISLPED 2006, Tegernsee, Germany

15. Input-specific optimization • Why do we need a tuning factor • Dominating path affects critical delay distribution Can be [1,41] Dominating path 41 0 1 1 1 0 1 Fei Hu, ISLPED 2006, Tegernsee, Germany

16. Outline • Background • Dynamic power dissipation • Glitch reduction • Previous LP model with fixed gate delay • Process-variation-resistant LP model • Input-specific optimization • Without process-variation • With process-variation • Experimental results • Conclusion Fei Hu, ISLPED 2006, Tegernsee, Germany

17. Experimental results • Experimental procedure • Power estimation • Event driven logic simulation • Fanout weighted sum of switching activities • Monte-Carlo simulation with 1,000 samples of delays under process-variation • Results analysis • Un-Opt., unit-delay circuit • Opt1, previous basic LP model w/ fixed gate delay • Opt2, Process-variation-resistant LP model • IS-Opt1, IS-Opt2, Input-specific optimizations Fei Hu, ISLPED 2006, Tegernsee, Germany

18. Experimental results – input-specific optimization • Application to “Opt1” (basic LP model), IS-Opt1 Fei Hu, ISLPED 2006, Tegernsee, Germany

19. Experimental results – input-specific optimization • Application to “Opt2” under process-variation, IS-Opt2 under 15% intra-die and 5% inter-die variation Fei Hu, ISLPED 2006, Tegernsee, Germany

20. Experimental results – input-specific optimization • Critical delay • Similar performance for “Opt2” and “IS-Opt2” Nominal delay Max. deviation Fei Hu, ISLPED 2006, Tegernsee, Germany

21. Outline • Background • Dynamic power dissipation • Glitch reduction • Previous LP model with fixed gate delay • Process-variation-resistant LP model • Input-specific optimization • Without process-variation • With process-variation • Experimental results • Conclusion Fei Hu, ISLPED 2006, Tegernsee, Germany

22. Conclusions • Explored a new aspect of low-power optimization for VLSI circuits • The input-specific Optimization • Optimizing the circuit for a given input sequence that may be specified for the circuit. • Defined the concept of glitch-generation probability • adaptively relax glitch-filtering constraints • Experimental results • Better solution with fewer delay buffers • Maintain similar power reduction and delay performance • Up to 80% and 63% reductions in delay buffers Fei Hu, ISLPED 2006, Tegernsee, Germany

23. Q & A Fei Hu, ISLPED 2006, Tegernsee, Germany

24. Backups

25. Process and delay variations • Process variations • Variations due to semiconductor process • VT, tox, Leff, Wwire, THwire,etc. • Inter-die variation • Constant within a die, vary from one die to another die of a wafer or wafer lot • Intra-die variation • Variation within a die • Due to equipment limitations or statistical effects in the fabrication process, e.g., variation in doping concentration • Spatial correlations and deterministic variation due to CMP and optical proximity effect Fei Hu, ISLPED 2006, Tegernsee, Germany

26. Delay model and implications • Random gate delay model • Truncated normal distribution • Assume independence • Variation in terms of σ/Dnom,i ratio • Effect of inter-die variations • Depends on its effect to switching activities • Definition of glitch-filtering probability Pglt = P {t2-t1< d} • Signal arrival time t1, t2 • Gate inertial delay d • Theorem 1 states the change of Pglt due to inter-die variation • erf(), the error function • k, a path and gate dependent constant • r,σ/Dnom,i ratio for inter-die variations Fei Hu, ISLPED 2006, Tegernsee, Germany

27. Delay model and implications • Process-variation-resistant design • Can be achieved by path balancing and glitch filtering • Critical delay may increase • Theorem 2 states that a solution is guaranteed only if circuit delay is allowed to increase • Proved by example, assuming 10% variation 3.9 2.1 Fei Hu, ISLPED 2006, Tegernsee, Germany

28. LP model based on statistical timing • Statistical timing model with random variables Fei Hu, ISLPED 2006, Tegernsee, Germany

29. LP model based on statistical timing • Minimum-maximum statistics • needed for tbi, Tbi • Previous works • Min, Max for two normal random variable not necessarily distributed as normal • Can be approximated with a normal distribution • Requiring complex operations, e.g., integration, exponentiation, etc. • Challenges for LP approach • Require simple approximation w/o nonlinear operations • Our approximation for C=Max(A,B), A, B, and C are Gaussian RVs Fei Hu, ISLPED 2006, Tegernsee, Germany

30. LP model based on statistical timing • Min-Max statistics approximation error • Negligible when |A-B|> 3(σA+ σB) • Largest when A=B Fei Hu, ISLPED 2006, Tegernsee, Germany

31. LP model based on statistical timing • Variables • Timing, delay variables with mean  and std dev σ • Auxiliary variables, • Constraints • Gate constraints • Timing window at the inputs for a two-input gate i • Timing window at outputs Fei Hu, ISLPED 2006, Tegernsee, Germany

32. LP model based on statistical timing • Constraints • Gate constraint • Linear approximation • k  [0.707, 1]; choose k=0.85, since • Glitch filtering constraints • Circuit delay constraint Fei Hu, ISLPED 2006, Tegernsee, Germany

33. LP model based on statistical timing • Parameter • r, σ/Dnom,i ratio • Dmax, circuit delay parameter • , optimism factor • =1, no relaxation • <1, optimistic about the actual glitch width • =0, reduce to previous model • Objective • Minimize #buffer inserted – sum of buffer delays Fei Hu, ISLPED 2006, Tegernsee, Germany