Low Power via Sub-Threshold Circuits

1. Low Power viaSub-Threshold Circuits Mike Pridgen

2. “Logic Circuits Operating in Subthreshold Voltages” • Jabulani Nyathi and Brent Bero • “Sub-Threshold Design: The Challenges of Minimizing Circuit Energy” • B.H. Calhoun, A. Wang, N. Verma, and A. Chandrakasan 2

3. Goal of Sub-Threshold Circuits • Minimize energy • Utilize leakage currents • Sacrifice speed 3

4. Uses of Sub-Threshold Circuits • Standalone, low power devices • Wireless sensor nodes • RFID tags • Burst-mode applications • Short, intensive bursts • Long, near-idle periods 4

5. Sub-Threshold FFT • 16 bit FFT • FFT lengths of 128 to 1024 • 350mV VDD • 10kHz • 155nJ / FFT • 350x better than microprocessor • 8x better than ASIC 5

6. Improving Performance by Changing VBULK • nMos • VBULK = 600mV • pMos • VBULK = 0V • 0 – 380mV • ID increases by 10x • Never “OFF” • ID > 0.1nA 6

7. Body Biasing Types • Traditional • Three main variations • SBB • DTMOS • ABB • Plus many others 7

8. Traditional Biasing • nMos VBULK = GND • pMOS VBULK = VDD Traditional CMOS Inverter 8

9. Switched Body Biasing • nMos VBULK = VDD • pMos VBULK = GND • VDD < VTH SBB CMOS Inverter 9

10. Dynamic Threshold • VBULK = VG • Off if VDD > VTH DTMOS Inverter 10

11. Adjustable Bulk Bias • VDD < VTH • VDD > VTH • Tunable • Low Power • High Speed • TBB TBB Inverter 11

12. Shorter Delays • 6 – 10x speedup 12

13. Improving Performance • Increased VDD = Increased Speed • VDD = .75VTH versus VDD = .5VTH • 8x faster • Bias scheme irrelevant • More power 13

14. Noise Effects • TBB versus Traditional • VDD = 376.2mV • Logic 0 • 0 to 200mV • Logic 1 • 225 to 376.2mV • SBB noise margins worse 14

15. Standard (6T) SRAM • Adjacent cells leakage current • Fails Static Noise Margins 15

16. Conclusions • Bias schemes increase performance • Speed versus Power • Slight increase in noise • 6T SRAMS unusable 16

17. Questions