Simultaneous supply threshold and width optimization for low power cmos circuits
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Simultaneous Supply, Threshold and Width Optimization for Low-Power CMOS Circuits. With an aside on System based shutdown. Gord Allan PhD Candidate ASIC Design. Factors vs Power and Delay. Changing VDD Dyn Stat Delay Supply.

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Simultaneous Supply, Threshold and Width Optimization for Low-Power CMOS Circuits

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Simultaneous supply threshold and width optimization for low power cmos circuits

Simultaneous Supply, Threshold and Width Optimization for Low-Power CMOS Circuits

With an aside on System based shutdown.

Gord AllanPhD CandidateASIC Design


Factors vs power and delay

Factors vs Power and Delay

  • Changing VDD Dyn Stat DelaySupply

  • Changing Vt Dyn Stat DelayThreshold

  • Changing Width W Dyn Stat Delay

Delay = A *C/(V*K)Pload = C*V2Psc = f(tr/f)*f(V3)*f(K)Pstat = Ileak*V

Where: A = 1/(1-n) * [2n/(1-n) + ln(3-4n)], n=Vt/VDD


Reducing vt and vdd

Reducing Vt and VDD

  • Lower Vt so that we can reduce VDD further

  • Ideal when Power Dynamic = Power Static

Example: - 600 gates - 18 gates deep - Critical Delay = 3.3 ns

VtVDDStaticDynTotal0.72.5V.03aW 260fW260fW

0.130.4V9 fW6 fW15fW

StaticPower

Vt


An aside system shutdown

An Aside: System Shutdown

  • If you’re not using something - TURN it OFF!

  • If it dosen’t need speed, TURN it DOWN!Aka. “Predictive System Shutdown and Other Architectural Techniques for Energy Efficient Programmable Computation,” Srivastava, et al.

  • But When and How?

  • When - Using user history to predict best time to sleep- There are costs (time and power) to go to sleep/awake- Voltage regulation problems.

  • How- Hard Enough in normal circuits (clock gating, supply red)- What to do when dynamic power is an issue? (cutting off VDD is tough and poses other problems)


Back to optimization

4*2/3 = 2.7 nS

1.3 nS

2 ns

E(2)

E(2)

F(1)

F(1)

G(1)

G(1)

2 nS

4 nS

C(1)

C(1)

D(1)

D(1)

A(2)

A(2)

1 nS

1 nS

B(4)

B(4)

2 ns

H(1)

H(1)

2 ns

I(1)

I(1)

Back to Optimization

  • How do we pick VDD, Vt, and Ws given a clk freq?

  • Draw Circuit

  • Assign Delay Estimates (based on fan-out)

  • Find Critical Path

  • Assign Maximum Delays (weighted to estimates) along most critical path

Eg. Tclk = 8 ns

  • Assign Maximum Delays to other gates on next most critical path, etc...


Pseudo code procedure

Pseudo-Code Procedure

for(VDD from 0.1 to 3.3) for(Vt from 0.1 to 0.7) for each gate for(W from 1 to 100) calculate delay if lower than Dmax pick W calculate total power dissipation

  • Gives optimal VDD, Vt and W for all gates such that timing is met. NB: Pwr - f(switching activity)

  • Complexity depends on number of gates and quantization of parameters

  • Binary Search technique is used for large circuits


Results

Results

Circuit A: s349 - 226 gates, depth 28Benchmark: Vdd=3.3V, Vt=0.7V  = 0.5Optimum: Vdd=0.7V, Vt=0.1VPower Savings of 54x

Circuit B: s526 - 596 gates, depth 18 Benchmark: Vdd=2.5V, Vt=0.7V  = 0.005Optimum: Vdd=0.4V, Vt=0.13V Power Savings of 18x


Problems for future work

Problems for Future Work

  • Perception - Static power is Bad!

  • Shutdown

  • Variation of low Vt due to process issues.- Drags improvements from 20x to 6x with 50% variation- How do we get a reliable and efficient low Vt?

  • System on a chip supplies - want > 1V. Noise issues.

  • Variation of Switching activities and their effect.

  • Low Vt - Great for pass logic! Exploit the benefits.

  • Multiple Vt circuits - advantages?


Primary references

Primary References

  • “Simultaneous Power Supply, Threshold Voltage, and Transistor Size Optimization for Low-Power Operation of CMOS Circuits,” Pant, De, Chatterjee, IEEE Trans. on VLSI Systems, Vol. 6, No. 4, Dec 1998

  • “Predictive System Shutdown and Other Architectural Techniques for Energy Efficient Programmable Computation,” Srivastava, Chandrakasan, Brodersen, IEEE Trans. on VLSI Systems Vol. 4, No.1, March 1996


Appendix more results

Appendix: More Results

Circuit A: s349 - 226 gates, depth 28Benchmark: Vdd=3.3V, Vt=0.7V  =0.5Optimum 1: Vdd=0.7V, Vt=0.1VSavings of: Power 54xArea of 64% =0.005Optimum 2: Vdd=0.6V, Vt=0.1V Savings of: Power 27x Area of 59%

Circuit B: s526 - 596 gates, depth 18 Benchmark: Vdd=2.5V, Vt=0.7V  = 0.5Optimum 1: Vdd=0.3V, Vt=0.1VSavings of: Power 67xArea of 8% = 0.005Optimum 2: Vdd=0.4V, Vt=0.13V Savings of: Power 18xArea of 20%


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