Simultaneous Supply, Threshold and Width Optimization for Low-Power CMOS Circuits. With an aside on System based shutdown. Gord Allan PhD Candidate ASIC Design. Factors vs Power and Delay. Changing VDD Dyn Stat Delay Supply.
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With an aside on System based shutdown.
Gord AllanPhD CandidateASIC Design
Delay = A *C/(V*K) Pload = C*V2 Psc = f(tr/f)*f(V3)*f(K)Pstat = Ileak*V
Where: A = 1/(1-n) * [2n/(1-n) + ln(3-4n)], n=Vt/VDD
Example: - 600 gates - 18 gates deep - Critical Delay = 3.3 ns
Vt VDD Static Dyn Total0.7 2.5V .03aW 260fW 260fW
0.13 0.4V 9 fW 6 fW 15fW
4*2/3 = 2.7 nS Low-Power CMOS Circuits
I(1)Back to Optimization
Eg. Tclk = 8 ns
for(VDD from 0.1 to 3.3) for(Vt from 0.1 to 0.7) for each gate for(W from 1 to 100) calculate delay if lower than Dmax pick W calculate total power dissipation
Circuit A: s349 - 226 gates, depth 28 Benchmark: Vdd=3.3V, Vt=0.7V = 0.5 Optimum: Vdd=0.7V, Vt=0.1V Power Savings of 54x
Circuit B: s526 - 596 gates, depth 18 Benchmark: Vdd=2.5V, Vt=0.7V = 0.005 Optimum: Vdd=0.4V, Vt=0.13V Power Savings of 18x
Circuit A: s349 - 226 gates, depth 28 Benchmark: Vdd=3.3V, Vt=0.7V =0.5 Optimum 1: Vdd=0.7V, Vt=0.1V Savings of: Power 54x Area of 64% =0.005 Optimum 2: Vdd=0.6V, Vt=0.1V Savings of: Power 27x Area of 59%
Circuit B: s526 - 596 gates, depth 18 Benchmark: Vdd=2.5V, Vt=0.7V = 0.5 Optimum 1: Vdd=0.3V, Vt=0.1V Savings of: Power 67x Area of 8% = 0.005 Optimum 2: Vdd=0.4V, Vt=0.13V Savings of: Power 18x Area of 20%