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Chapter 3

## Chapter 3

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1. Chapter 3 Combinational Logic By Taweesak Reungpeerakul

2. Contents • Basic Combinational Logic Circuits • Implement SOP and POS using Basic Logic Gates • Universal Property of NAND and NOR • Combinational Logic using NAND and NOR • Operation with Pulse Waveforms • Digital System Application 242-208 CH3

3. Inputs A B C AB AC BC OUT 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 1 0 0 1 1 1 0 0 0 0 0 0 1 0 1 0 1 0 1 1 1 0 1 0 0 1 1 1 1 1 1 1 1 3.1 Basic Combinational Logic Circuit AB AC BC AB+AC+BC 242-208 CH3

4. AND-OR-INV Logic Invert AND-OR in SOP  AND-OR-INV in POS AB+AC+BC =(A+B)(A+C)(B+C) 242-208 CH3

5. XOR OUT = AB + AB 242-208 CH3

6. XNOR OUT = AB + AB = AB + AB 242-208 CH3

7. Ex#1: OUT = ABC+DE Ex#2: OUT = A(BC+DE) 3.2 Implementing Combinational Logic 242-208 CH3

8. From Truth Table Truth Table A B C OUT 0 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 0 242-208 CH3

9. Example TableLogic Circuit  Karnaugh Map  Simplified Circuit Truth Table A B C OUT 0 0 0 1 0 0 1 1 0 1 0 0 0 1 1 0 1 0 0 0 1 0 1 1 1 1 0 0 1 1 1 1 242-208 CH3

10. INV, OR, AND, and NOR created by using NAND gates 2.3 Universal Property of NAND&NOR AND INV OR NOR 242-208 CH3

11. INV, OR, AND, and NAND created by using NOR gates Universal Property of NOR AND INV OR NAND 242-208 CH3

12. 3.4 Combinational Logic using NAND & NOR • NAND; OUT = AB+CD = AB+CD= (AB)(CD) 242-208 CH3

13. Dual Symbols of NAND Always use the gate symbols in such a way that every connection between a gate output and a gate input is either bubble-to-bubble or nonbubble-to-nonbubble. AB+C ABC 242-208 CH3

14. Example: implemented by NAND • Ex2: ABC+D+E • Ex1: ABC+DE 242-208 CH3

15. Combinational Logic using NOR • NOR; (A+B)(C+D) = (A+B)(C+D)= (A+B)+(C+D) 242-208 CH3

16. Dual Symbols (A+B)+C (A+B)C 242-208 CH3

17. 3.5 Operation with Pulse Waveforms Logic circuit  Timing diagram D C 242-208 CH3

18. Develop logic circuit from waveforms 242-208 CH3

19. Functions of Combinational Logic (Session 2) • Adders • Comparators • Decoders • Encoders • Code Converters • Multiplexers • Demultiplexers 242-208 CH3

20. Full Adder A B Cin SUM Cout 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 3.6 Basic Adders Half Adder A B SUM Cout 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 SUM = AB Cout = AB SUM = ABCin Cout = AB+(AB)Cin 242-208 CH3

23. 3.7 Parallel Binary Adder A full adder is required for each bit in the numbers. A2A1 + B2B1 S3S2S1 Question: 4-bit numbers 242-208 CH3

24. 4-bit Parallel Adders An Bn Cn-1 Sn Cn 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1 242-208 CH3

25. IC:4-bit Parallel Adder Example: 74LS83A (or 74LS283) 74LS83A 74LS283 Question: Show circuit diagram of A+B by using 74LS83A. A = 00001111 and B = 01011100 242-208 CH3

26. COMP A0 0 A1 A A2 A3 3 A > B A > B Cascading inputs A = B A = B A < B A < B B0 0 B B1 B2 B3 3 3.8 Comparators • Inequality • IC: 74LS85 • Equality • Comparing A and B: AB • If A=B, output = 0 • If A≠B, output = 1 • HIGH indicates equality: AB (XNOR) • A1A0 ? B1B0 Outputs Question:Show circuit diagram in order to compare two 8-bit numbers by using 74LS85. 242-208 CH3

27. LSBs MSBs A0 A4 COMP COMP 0 0 A1 A5 A2 A6 A A A3 A7 3 3 A > B A > B A > B A > B +5.0 V Outputs A = B A = B A = B A = B A < B A < B A < B A < B B0 B4 0 0 A A B1 B5 B2 B6 B3 3 B7 3 Two 74LS85 Cascaded Arrangement 242-208 CH3

28. 74HC85 Truth Table 242-208 CH3

29. 3.9 Decoders • A decoder is a logic circuit that detects the presence of a specific combination of bits at its input. A0 A0 OUT OUT A1 A1 A2 A2 A3 A3 Active HIGH decoder for 0011 Active LOW decoder for 0011 242-208 CH3

30. 4-to-16 Decoder A0 A1 A2 A3 CS1 CS2 IC: 74HC154 Question:Use 74HC154 to implement the logic in order to support a 5-bit number. 242-208 CH3

31. BCD-to-Decimal Decoder • BCD-to-decimal decoders accept a binary coded decimal input and activate one of ten possible decimal digit indications. • IC: 74HC42 Question:Assume the inputs to the 74HC42 decoder are the sequence 0101, 0110, 0011, and 0010. Describe the output. A0 Answer:All lines are HIGH except for one active output, which is LOW. The active outputs are 5, 6, 3, and 2 in that order. A1 A2 A3 Question:Write truth table of output 0. 242-208 CH3

32. IC: 74LS47 BCD Inputs (D-A) 7-segment Outputs (a -g) Ripple Blanking Input (RBI) Blanking Input/Ripple Blanking Output (BI/RBO) Lamp Test (LT) Zero Suppression BCD-to-7-Segment Decoder VCC BCD/7-seg BI/RBO BI/RBO BCD inputs Outputs to seven segment device LT LT RBI RBI 74LS47 GND 242-208 CH3

33. Illustration of Leading Zero Suppression 242-208 CH3

34. Illustration of Trailing Zero Suppression 242-208 CH3

35. An encoder accepts an active logic level on one of its inputs representing a digit, such as a decimal or octal digits, and converts it to a coded output, such as BCD or binary. IC: 74HC147 16-to-4 encoder (decimal-to-BCD) IC: 74F148 8-to-3 encoder 3.10 Encoders 1 A0 2 3 A1 4 5 A2 6 7 8 A3 9 242-208 CH3

36. 0 0 1 0 0 0 0 0 0 Example • Show how the decimal-to-BCD encoder converts the decimal number 3 into a BCD 0011. 1 1 A0 2 3 1 A1 4 0 5 A2 6 7 8 0 A3 9 242-208 CH3

37. The 74HC147 is an example of an IC encoder. It has ten active-LOW inputs and converts the active input to an active-LOW BCD output. This device offers additional flexibility with a priority encoder. 74HC147 VCC HPRI/BCD Decimal input BCD output GND 74HC147 242-208 CH3

38. A Simplified Keyboard Encoder VCC BCD complement of key press The zero line is not needed by the encoder, but may be used by other circuits to detect a key press. 242-208 CH3

39. BCD-to-BIN Conversion IC: 74184 BIN-to-BCD Conversion IC: 74185 3.11 Code Converters 242-208 CH3

40. BIN-to-Gray Gray-to-BIN Code Converters (cont.) LSB G0 LSB B0 B0 G0 B1 G1 B1 G1 B2 B2 G2 G2 B3 G3 B3 G3 MSB MSB Question:Show the conversion of binary 0111 to Gray and vice versa. 242-208 CH3

41. A multiplexer has several data-input lines and a single output line. It also has data-select inputs, which permit digital data on any one of the inputs to be switched to the output line. Another name is a data selector. IC: 74HC157 Quad 2-input MUX IC: 74HC151 8-input MUX 3.12 Multiplexers (MUX) 0 S0 Data select 1 S1 Data output D0 D1 Data inputs D2 D3 Question:Which data line is selected if S1S0 = 10? 242-208 CH3

42. 74HC157 Quad 2-input MUX 74HC151 8-input MUX ICs 242-208 CH3

43. A DEMUX basically reverses the multiplexing function. It takes data from one input line and distributes to one of output lines depending on the select lines. Another name is a data distributor. IC: 74LS138 8-output DEMUX 3.13 Demultiplexers (DEMUX) 74LS138 0 Data select lines 1 0 Data outputs Enable inputs Question:Which data output is selected if A2A1A0 = 010? 242-208 CH3

44. Determine the outputs, given the inputs shown. Example (DEMUX) A 0 A 1 A 2 G 1 LOW G 2A LOW G 2B Y 0 Y Data select lines 1 Y 2 Data outputs Y 3 Y Enable inputs 4 Y 5 Y 6 74LS138 Y 7 242-208 CH3