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Chapter 3. Arithmetic for Computers. Arithmetic for Computers. §3.1 Introduction. Operations on integers Addition and subtraction Multiplication and division Dealing with overflow Floating-point real numbers Representation and operations. operation. a. ALU. 32. result. 32. b. 32.

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**Chapter 3**Arithmetic for Computers**Arithmetic for Computers**§3.1 Introduction • Operations on integers • Addition and subtraction • Multiplication and division • Dealing with overflow • Floating-point real numbers • Representation and operations Chapter 3 — Arithmetic for Computers — 2**operation**a ALU 32 result 32 b 32 Arithmetic • Where we've been: • Performance (seconds, cycles, instructions) • Abstractions: Instruction Set Architecture Assembly Language and Machine Language • What's up ahead: • Implementing the Architecture**Numbers**• Bits are just bits (no inherent meaning) — conventions define relationship between bits and numbers • Binary numbers (base 2) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001... decimal: 0...2n-1 • Of course it gets more complicated: numbers are finite (overflow) fractions and real numbers negative numbers e.g., no MIPS subi instruction; addi can add a negative number) • How do we represent negative numbers? i.e., which bit patterns will represent which numbers?**Possible Representations**• Sign Magnitude: One's Complement Two's Complement 000 = +0 000 = +0 000 = +0 001 = +1 001 = +1 001 = +1 010 = +2 010 = +2 010 = +2 011 = +3 011 = +3 011 = +3 100 = -0 100 = -3 100 = -4 101 = -1 101 = -2 101 = -3 110 = -2 110 = -1 110 = -2 111 = -3 111 = -0 111 = -1 • Issues: balance, number of zeros, ease of operations • Which one is best? Why?**maxint**minint MIPS 32-bit Signed Integer 0000 0000 0000 0000 0000 0000 0000 0000two = 0ten0000 0000 0000 0000 0000 0000 0000 0001two = + 1ten0000 0000 0000 0000 0000 0000 0000 0010two = + 2ten...0111 1111 1111 1111 1111 1111 1111 1110two = + 2,147,483,646ten0111 1111 1111 1111 1111 1111 1111 1111two = + 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0000two = – 2,147,483,648ten1000 0000 0000 0000 0000 0000 0000 0001two = – 2,147,483,647ten1000 0000 0000 0000 0000 0000 0000 0010two = – 2,147,483,646ten...1111 1111 1111 1111 1111 1111 1111 1101two = – 3ten1111 1111 1111 1111 1111 1111 1111 1110two = – 2ten1111 1111 1111 1111 1111 1111 1111 1111two = – 1ten**Two's Complement Operations**• Negating a two's complement number: invert all bits and add 1 • remember: “negate (+/-)” and “invert (1/0)” are quite different! • Converting n bit numbers into numbers with more than n bits: • MIPS 16 bit immediate gets converted to 32 bits for arithmetic • copy the most significant bit (the sign bit) into the other bits 0010 -> 0000 0010 1010 -> 1111 1010 • "sign extension" • MIPS: lbu vs. lb • ARM: LDRSB vs LDRB**Addition & Subtraction**• Just like in grade school (carry/borrow 1s) 0111 0111 0110+ 0110 - 0110 - 0101 • Two's complement operations easy • subtraction using addition of negative numbers 0111 + 1010 • Overflow (result too large for finite computer word): • e.g., adding two n-bit numbers does not yield an n-bit number 0111 + 0001 note that overflow term is somewhat misleading, 1000 it does not mean a carry “overflowed”**Effects of Overflow**• An exception (interrupt) occurs • Control jumps to predefined address for exception • Interrupted address is saved for possible resumption • Details based on software system / language • example: flight control vs. homework assignment • Don't always want to detect overflow — new MIPS instructions: addu, addiu, subu note: addiu still sign-extends! note: sltu, sltiu for unsigned comparisons — ARM instructions: ADD, SUB • Roll over:circular buffers • Saturation: pixel lightness control**Review: Boolean Algebra & Gates**• Problem: Consider a logic function with three inputs: A, B, and C. Output D is true if at least one input is true Output E is true if exactly two inputs are true Output F is true only if all three inputs are true • Show the truth table for these three functions. • Show the Boolean equations for these three functions. • Show an implementation consisting of inverters, AND, and OR gates.**operation**op a b res result An ALU (arithmetic logic unit) • Let's build an ALU to support the andi and ori instructions • we'll just build a 1 bit ALU, and use 32 of them • Possible Implementation (sum-of-products): a b**S**A C B Review: The Multiplexor • Selects one of the inputs to be the output, based on a control input • Lets build our ALU using a MUX: note: we call this a 2-input mux even though it has 3 inputs! 0 1**Different Implementations**• Not easy to decide the “best” way to build something • Don't want too many inputs to a single gate • Dont want to have to go through too many gates • for our purposes, ease of comprehension is important • Let's look at a 1-bit ALU for addition: • How could we build a 1-bit ALU for add, and, and or? • How could we build a 32-bit ALU? cout = a b + a cin + b cin sum = a xor b xor cin**Building a 32 bit ALU**Case (Op) { 0: R = a ^ b; 1: R = a V b; 2: R = a + b} R0 = a ^ b; R1 = a V b; R2 = a + b; Case (Op) { 0: R = R0; 1: R = R1; 2: R = R2 }**What about subtraction (a – b) ?**• Two's complement approach: just negate b and add. • How do we negate? • A very clever solution: Result = A + (~B) + 1**Tailoring the ALU to the MIPS**• Need to support the set-on-less-than instruction (slt) • remember: slt is an arithmetic instruction • produces a 1 if rs < rt and 0 otherwise • use subtraction: (a-b) < 0 implies a < b • Need to support test for equality (beq $t5, $t6, $t7) • use subtraction: (a-b) = 0 implies a = b**B**i n v e r t O p e r a t i o n C a r r y I n a 0 1 R e s u l t b 0 2 1 L e s s 3 a . C a r r y O u t B i n v e r t O p e r a t i o n C a r r y I n a 0 1 R e s u l t b 0 2 1 L e s s 3 S e t O v e r f l o w O v e r f l o w d e t e c t i o n b . Supporting slt • Can we figure out the idea?**B**i n v e r t O p e r a t i o n C a r r y I n a 0 1 R e s u l t b 0 2 1 L e s s 3 a . C a r r y O u t Test for equality • Notice control lines:000 = and001 = or010 = add110 = subtract111 = slt • Note: zero is a 1 when the result is zero!**Conclusion**• We can build an ALU to support the MIPS instruction set • key idea: use multiplexor to select the output we want • we can efficiently perform subtraction using two’s complement • we can replicate a 1-bit ALU to produce a 32-bit ALU • Important points about hardware • all of the gates are always working • the speed of a gate is affected by the number of inputs to the gate • the speed of a circuit is affected by the number of gates in series (on the “critical path” or the “deepest level of logic”) • Our primary focus: comprehension, however, • Clever changes to organization can improve performance (similar to using better algorithms in software) • we’ll look at two examples for addition and multiplication**Problem: ripple carry adder is slow**• Is a 32-bit ALU as fast as a 1-bit ALU? • Is there more than one way to do addition? • two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? c1 = b0c0 + a0c0 +a0b0 c2 = b1c1 + a1c1 +a1b1 c3 = b2c2 + a2c2 +a2b2 c4 = b3c3 + a3c3 +a3b3 Expanding the carry chains… c2 = a1a0b0+a1a0c0+a1b0c0+b1a0b0+b1a0c0+b1b0c0+a1b1 c3 = ??? c4 = ??? Not feasible! Why? Cn has 2P terms(P=0…n)**Carry-lookahead adder**• An approach in-between our two extremes • Motivation: • If we didn't know the value of carry-in, what could we do? • When would we always generate a carry? gi = ai bi • When would we propagate the carry? pi = ai + bi • Did we get rid of the ripple? c1 = g0 + p0c0 c2 = g1 + p1c1 c3 = g2 + p2c2 c4 = g3 + p3c3 Expanding the carry chains… c2 = g1+p1g0+p1p0c0 Feasible! Why? The carry chain does not disappear, but is much smaller: Cn has n+1 terms**P0 = p3 p2 p1 p0**P1 = p7 p6 p5 p4 P2 =p11 p10 p9 p8 P3 = p15 p14 p13 p12 G0 = g3+p3g2+p3p2g1+p3p2p1g0 G1 = g7+p7g6+p7p6g5+p7p6p5g4 G2 = g11+p11g10+p11p10g9+p11p10p9g8 G3 = g15+p15g14+p15p14g13+p15p14p13g12 Use principle to build bigger adders • How about constructing a 16-bit adder in CLA way? • Can’t build a 16 bit adder this way... (too big) • Could use ripple carry of 4-bit CLA adders • Better: use the CLA principle again! C1 = G0 +(P0 ⋅ c0) C2 = G1+(P1 ⋅ G0)+(P1⋅P0⋅c0) C3 = G2+(P2 ⋅ G1)+(P2⋅P1⋅G0)+(P2⋅P1⋅P0⋅c0) C4 = G3+(P3 ⋅ G2)+(P3⋅P2⋅G1)+(P3⋅P2⋅P1⋅G0) +(P3⋅P2⋅P1⋅P0⋅c0)**Dealing with Overflow (ARM)**• Some languages (e.g., C) ignore overflow • Use ARM ADD,SUB instructions • Other languages (e.g., Ada, Fortran) require raising an exception • Use ARM ADDS,SUBS instructions • On overflow, invoke exception handler Chapter 3 — Arithmetic for Computers — 31**Multimedia Support in Modern Instruction Sets**Chapter 3 — Arithmetic for Computers — 33**1000**× 1001 1000 0000 0000 1000 1001000 Multiplication §3.3 Multiplication • Start with long-multiplication approach multiplicand multiplier product Length of product is the sum of operand lengths Chapter 3 — Arithmetic for Computers — 34**Multiplication Hardware**Initially 0 Chapter 3 — Arithmetic for Computers — 35**Optimized Multiplier**• Perform steps in parallel: add/shift • One cycle per partial-product addition • That’s ok, if frequency of multiplications is low Chapter 3 — Arithmetic for Computers — 36**Faster Multiplier**• Uses multiple adders • Cost/performance tradeoff • Can be pipelined • Several multiplication performed in parallel Chapter 3 — Arithmetic for Computers — 37**MIPS Multiplication**• Two 32-bit registers for product • HI: most-significant 32 bits • LO: least-significant 32-bits • Instructions • mult rs, rt / multu rs, rt • 64-bit product in HI/LO • mfhi rd / mflo rd • Move from HI/LO to rd • Can test HI value to see if product overflows 32 bits • mul rd, rs, rt • Least-significant 32 bits of product –> rd Chapter 3 — Arithmetic for Computers — 38**ARM Multiplication**• The MUL instruction is used to multiply signed or unsigned variables to produce a 32-bit result • Instruction • MUL Rd,Rm,Rs ; Rd = Rm * Rs (32 bits) • Because the MUL instruction produces only the lower 32 bits of the 64-bit product, MUL gives the same answer for both signed and unsigned numbers Chapter 3 — Arithmetic for Computers — 39**Division**§3.4 Division • Check for 0 divisor • Long division approach • If divisor ≤ dividend bits • 1 bit in quotient, subtract • Otherwise • 0 bit in quotient, bring down next dividend bit • Restoring division • Do the subtract, and if remainder goes < 0, add divisor back • Signed division • Divide using absolute values • Adjust sign of quotient and remainder as required • Remainder and dividend must have the same sign! • EX: (-7)÷(+2) = (-3)x2 + (-1) or (-4)x2+(+1) ??? quotient dividend 1001 1000 1001010 -1000 10 101 1010 -1000 10 divisor remainder n-bit operands yield n-bitquotient and remainder Chapter 3 — Arithmetic for Computers — 40**Division Hardware**Initially divisor in left half Initially dividend Chapter 3 — Arithmetic for Computers — 41**Optimized Divider**• One cycle per partial-remainder subtraction • Looks a lot like a multiplier! • Same hardware can be used for both Chapter 3 — Arithmetic for Computers — 42**Faster Division**• Can’t use parallel hardware as in multiplier • Subtraction is conditional on sign of remainder • Faster dividers (e.g. SRT devision) generate multiple quotient bits per step • Still require multiple steps Chapter 3 — Arithmetic for Computers — 43**MIPS Division**• Use HI/LO registers for result • HI: 32-bit remainder • LO: 32-bit quotient • Instructions • div rs, rt / divu rs, rt • No overflow or divide-by-0 checking • Software must perform checks if required • Use mfhi, mflo to access result Chapter 3 — Arithmetic for Computers — 44**ARM Division**• The classic ARM instruction set does not include divide instruction • ARMv7R and ARMv7M include • Signed integer divide - SDIV • Unsigned integer divide - UDIV Chapter 3 — Arithmetic for Computers — 45**Floating Point**§3.5 Floating Point • Representation for non-integral numbers • Including very small and very large numbers • Like scientific notation • –2.34 × 1056 • +0.002 × 10–4 • +987.02 × 109 • In binary • ±1.xxxxxxx2 × 2yyyy • Types float and double in C normalized not normalized Chapter 3 — Arithmetic for Computers — 46**Floating Point Standard**• Defined by IEEE Std 754-1985 • Developed in response to divergence of representations • Portability issues for scientific code • Now almost universally adopted • Two representations • Single precision (32-bit) • Double precision (64-bit) Chapter 3 — Arithmetic for Computers — 47**IEEE Floating-Point Format**• S: sign bit (0 non-negative, 1 negative) • Normalize significand: 1.0 ≤ |significand| < 2.0 • Always has a leading pre-binary-point 1 bit, so no need to represent it explicitly (hidden bit) • Significand is Fraction with the “1.” restored • Exponent: excess representation: actual exponent + Bias • Ensures exponent is unsigned • Single: Bias = 127; Double: Bias = 1203 single: 8 bitsdouble: 11 bits single: 23 bitsdouble: 52 bits S Exponent Fraction Chapter 3 — Arithmetic for Computers — 48**Single-Precision Range**• Exponents 00000000 and 11111111 reserved • Smallest value • Exponent: 00000001 actual exponent = 1 – 127 = –126 • Fraction: 000…00 significand = 1.0 • ±1.0 × 2–126 ≈ ±1.2 × 10–38 • Largest value • exponent: 11111110 actual exponent = 254 – 127 = +127 • Fraction: 111…11 significand ≈ 2.0 • ±2.0 × 2+127 ≈ ±3.4 × 10+38 Chapter 3 — Arithmetic for Computers — 49**Double-Precision Range**• Exponents 0000…00 and 1111…11 reserved • Smallest value • Exponent: 00000000001 actual exponent = 1 – 1023 = –1022 • Fraction: 000…00 significand = 1.0 • ±1.0 × 2–1022 ≈ ±2.2 × 10–308 • Largest value • Exponent: 11111111110 actual exponent = 2046 – 1023 = +1023 • Fraction: 111…11 significand ≈ 2.0 • ±2.0 × 2+1023 ≈ ±1.8 × 10+308 Chapter 3 — Arithmetic for Computers — 50**Floating-Point Precision**• Relative precision • all fraction bits are significant • Single: approx 2–23 • Equivalent to 23 × log102 ≈ 23 × 0.3 ≈ 6 decimal digits of precision • Double: approx 2–52 • Equivalent to 52 × log102 ≈ 52 × 0.3 ≈ 16 decimal digits of precision Chapter 3 — Arithmetic for Computers — 51**Floating-Point Example**• Represent –0.75 • –0.75 = (–1)1 × 1.12 × 2–1 • S = 1 • Fraction = 1000…002 • Exponent = –1 + Bias • Single: –1 + 127 = 126 = 011111102 • Double: –1 + 1023 = 1022 = 011111111102 • Single: 1011111101000…00 • Double: 1011111111101000…00 Chapter 3 — Arithmetic for Computers — 52**Floating-Point Example**• What number is represented by the single-precision float 11000000101000…00 • S = 1 • Fraction = 01000…002 • Fxponent = 100000012 = 129 • x = (–1)1 × (1 + 012) × 2(129 – 127) = (–1) × 1.25 × 22 = –5.0 Chapter 3 — Arithmetic for Computers — 53**IEEE 754 encoding of floating-point numbers**+ - + - + -**Floating-Point Addition**• Consider a 4-digit decimal example • 9.999 × 101 + 1.610 × 10–1 • 1. Align decimal points • Shift number with smaller exponent • 9.999 × 101 + 0.016 × 101 • 2. Add significands • 9.999 × 101 + 0.016 × 101 = 10.015 × 101 • 3. Normalize result & check for over/underflow • 1.0015 × 102 • 4. Round and renormalize if necessary • 1.002 × 102 Chapter 3 — Arithmetic for Computers — 57

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