Experiment

1. Experiment Previously: leakage current problem Capacitor measurement TFT measurement

2. Experiment Attempt to increase thickness (20 cycles) Particle deposition is problematic: more cycles →larger area is deposited with thick particles Thick, porous Another problem Surface is stained after H2O2 treatment →UV ozone treatment is tried

3. Experiment Intensive rinsing removes particle deposition but, new problem: After 2~3 cycles Losing hydrophilicity OH OH OH Adsorption is terminated: No deposition after 2~3 cycles → ~1nm thickness

4. Experiment Piranha solution cleaning Clean organics & form hydroxyl group on surface Results: Clean surface Hydrophilicity is sustained for repeated cycles → ~2.5nm thickness

5. Experiment Wafer scale deposition is failed by: again, particle deposition & elevated moisture level in glovebox (>50 ppm)

6. Experiment TFT measurement Gate is insulated at leakage current measurement & large Ig at transfer curve

7. Experiment Surface roughness may limit IDS Large Ig may be capacitive by insulated source, drain and gate Al2O3 Smoothing layer HfO2 HfO2 Si Si Sol-gel spin-coated Al2O3 Rough dielectric surface (RMS ~ 18Å) Surface roughness was measured by AFM

8. Experiment Surface roughness was larger than reference HfO2-Surface HfO2-SSG10: RMS = 4.1nm HfO2-Spin

9. Surface roughness was reduced after Al2O3 sol-gel spin coating Before RMS=4.1nm After Al2O3 spin-coating RMS=1.0nm

10. Experiment Normal probe tip Pt wire no IDS Good performance GIO GIO SiO2 SiO2 Si Si Sharp probe tip can contact Si through thin HfO2 dielectric But Pt wire was not appropriate for TFT measurement

11. Experiment Gate isolation Silicon oxide wafer SiO2 SiO2 SiO2 Buffered oxide etch Si Si Surface sol-gel Gate-probe tip is isolated! Buffered oxide etch SiO2 GIO SiO2 SiO2 SiO2 HfO2 HfO2 Si Si

12. Experiment Gate isolation Result: still have large leakage current - Chemical damage into SiO2 layer (during patterned BOE etching) Experiment for confirmation Current through thermal SiO2 SiO2 GIO SiO2 HfO2 Si

13. Future work Device fabrication Pattered ITO electrode Perfectly isolated gate Surface roughness Precursor solution filtering Cleaner drying environment Surface sol-gel active layer TiO2, SnO2, TixSn1-xO2 ITO Glass

14. Idea Vertically aligned NWs or NRs Unique properties: Ordered crystal orientation High aspect ratio Etc. Nanorod devices DSSC, Piezoelectric, FE devices are capacitor-configuration devices (MSM or MIM) - Device fabrication is easier

15. Idea ZnOnanorods for resistive memory Low voltage operation Device structure: Pt ZnO NR (Hydrothermal) >100 cycles endurance ITO >1000 sec retention

16. Idea Self-assembled nanorods for memory application Advantages: Ultra-high density :1010 bits/mm2 (Lithography-free) Reliable nanorod isolation High density is realized by Uniform & narrow diameter of NRs Device fabrication: Transfer & metallization Ag paste Substrate Substrate

17. Idea Device characterization CAFM measurement - Purely individual nanorod characterization Vertically aligned nanorods for Gigabit memory application