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Requirements on SVD2 readout. data processing speed greater than 1kHz dead time less than 5% at 1kHz trigger rate data size with a manageable level (~10MB/s) storage capability = 24MB/s SVD2 raw data size = 6kB/event/FADC x 1kHz x 36FADCs = 216MB/s  10MB/s with sparcification.

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Requirements on SVD2 readout


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    1. Requirements on SVD2 readout • data processing speed greater than 1kHz • dead time less than 5% at 1kHz trigger rate • data size with a manageable level (~10MB/s) • storage capability = 24MB/s • SVD2 raw data size = 6kB/event/FADC x 1kHz x 36FADCs = 216MB/s  10MB/s with sparcification

    2. Solutions for SVD2 readout • 54 (6+12+18+18) ladders • 216 Cat 5 cables (4ch/cable) • 36 FADCs (24ch/FADC) • 6kB raw data/FADC • 12 PCs (3 PCI cards/PC) • dual XEON 2.4GHz • intel compiler • software using Posix thread • PCI: 25MB/s max.  up to 4kHz for 6kB/FADC

    3. Overview of the data flow Cat. 5 cables x 216 One Cat. 5 cable transmits four VA1TA chip analog data The detector and frontend electronics FADC x 36 Read-out PC x 12 PCI card x 3 sparsification and data reformat ~6kB/event LVDS 24 VA1TA chip analog data (128 x 24 = 3072 strips) are digitized. The Belle Event builder

    4. Performance of SVD2 readout • event processing rate ~ {1400 – 45 x [occupancy(%)]} Hz e.g. > 1kHz at 5% occupancy • at 5% occupancy • data size = 10.4kB/event • event processing rate ~ 1.3kHz • deadtime ~ 5% or less • frontendbackend: 2.6% • rest: FADC keeping busy by instantanous high rate

    5. processing speed (Hz) Performances (processing speed) • We measured the processing speed by changing sparsification thresholds to vary the occupancy: • the speed : ~1.3kHz data size: 10.4kB measured dead time: ≲5% @ 5% occupancy. occupancy The SVD2 occupancy is estimated to be roughly 5% from the experience of the SVD1. data processing speed of the DAQ system including not only read-out PCs but also the Belle event builder

    6. Requirements on SVD2.5 readout • data processing speed greater than 3 kHz • dead time less than 5% ? at 3 kHz trigger rate • data size with a manageable level (~Y MB/s) • storage capability = 250MB/s (max) • SVD2.5 VA1TA raw data size = 6kB/event/FADC x 3 kHz x 32FADCs = 576MB/s  86MB/s with sparcification • occupancy ~ 15% • SVD2.5 APV25 raw data size (no-striplet option) = (6-18)kB/event/FADC x 3 kHz x 4FADCs = (72-216)MB/s  3 MB/s with sparcification • occupancy ~ 10% x 3 / 8 = 4% • assuming

    7. Solution for SVD2.5 readout1) VA part • 48 VA ladders • 192 Cat 5 cables (4ch/cable) • 32 FADCs (24ch/FADC) • 6kB raw data/FADC • 32 PCs (1 PCI card/PC) • dual XEON 3.6GHz • intel compiler • software using Posix thread • PCI: 75MB/s max.  up to 12kHz for 6kB/FADC

    8. Expected performance of SVD2.5 readout: 1) VA part • event processing rate ~ {6300 – 200 x [occupancy(%)]} Hz e.g. > 3kHz at 15% occupancy • at 15% occupancy • data size = 31.2kB/event • event processing rate ~ 3.3 kHz • deadtime ~ ? • frontendbackend: 7.8% • rest: FADC keeping busy by instantanous high rate

    9. Solution for SVD2.5 readout2) APV part coming soon