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FPGA Technology Mapping: A Study of Optimality

FPGA Technology Mapping: A Study of Optimality. Andrew C. Ling M.A.Sc. Candidate University of Toronto Deshanand P. Singh Ph.D. Altera Corporation Professor Stephen D. Brown Altera Corporation Toronto University of Toronto. Goals.

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FPGA Technology Mapping: A Study of Optimality

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  1. FPGA Technology Mapping: A Study of Optimality Andrew C. Ling M.A.Sc. CandidateUniversity of Toronto Deshanand P. Singh Ph.D. Altera Corporation Professor Stephen D. Brown Altera Corporation Toronto University of Toronto

  2. Goals • Determine how “good” current FPGA LUT based technology mappers are in terms of area-optimality • A. Farrahi and M. Sarrafzadeh (1994).Area problem shown to be NP-Hard

  3. Method • Take a set of benchmark circuits and technology map them to LUTs using one of the best existing LUT based technology mappers. • Devise a resynthesis technique that is able to remove LUTs from these pre-existing technology mapped circuit. • The more LUTs that can be removed, the farther the original technology mapping was from thearea-optimal solution.

  4. Resynthesis • Attempt to map a cone with X LUTs to another cone with less than X LUTs

  5. Sliding Window Approach • Resynthesize subcircuits • Does not give the globally optimal solution; however gives an indication of the area “left on the table”

  6. C1 C2 C3 Background: The Propositional Satisfiability (SAT) problem Given a formula, f : • Defined over a set of variables, V (a,b,c) • Comprised of a conjunction of clauses (C1,C2,C3) • Each clause is a disjunction of literals of the variables V SAT: Seek an assignment of to the variables, V, which sets expression to ‘1’. Example : a=b=c=1

  7. Construction of CNF • T. Larrabee, “Test pattern generation using Boolean satisfiability," TCAD, 1992 (Plaisted's and Greenbaum's encoding which is based on Tseitin's work) • Creates a Characteristic Function for circuits f=(x2+¬g) (x1+¬g) (¬x2+¬x1+g)

  8. Construction of CNF (cont’d) f AND= (x2+¬z1) (x1+¬z1) (¬x2+¬x1+ z1) f OR= (¬x3+g) (¬z1+g) (x3+z1+ ¬g) f total= fAND fOR = (x2+¬z1) (x1+¬z1) (¬x2+¬x1+ z1) (¬x3+g) (¬z1+g) (x3+z1+ ¬g)

  9. Formulating Resynthesis Problem 2-LUT f g 2-LUT 2-LUT 2-LUT ? 2-LUT • Can function fbe implemented in circuit g ? • Does there exist a configuration to gsuch that for all inputs to g, f is equivalent to g

  10. Formulating Resynthesis Problem 2-LUT f g 2-LUT 2-LUT 2-LUT ? 2-LUT • Derive characteristic function Hfor circuit g • Replace all instances of g in H with f • H[g/f](g ≡ f ) • f is equivalent to g

  11. Formulating Resynthesis Problem 2-LUT f g 2-LUT 2-LUT 2-LUT ? 2-LUT • Does there exist a configuration to gsuch that for all inputs to g, f is equivalent to g ? (g ≡ f )

  12. Formulating Resynthesis Problem 2-LUT f g 2-LUT 2-LUT 2-LUT ? 2-LUT • Does there exist a configuration to gsuch that for all inputs to g, f is equivalent to g ? E A l1…lmx1…xn(g ≡ f )

  13. Formulating Resynthesis Problem 2-LUT f g 2-LUT 2-LUT 2-LUT SAT 2-LUT • Express as a QBF with inputs (x1…xn) and configuration bits (l1…lm) l1…lmx1…xn(g ≡ f ) • Remove quantifiers to form a SAT problem(A. Biere. “Resolve and Expand”, SAT’04) E A

  14. Resynthesis Structures Used • Given a MFFC with 7 or less inputs and containing more than 2 LUTs, map it to: • Given a MFFC with 10 or less inputs and containing more than 3 LUTs, map it to: 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT 4-LUT

  15. Resynthesis Results, 4-LUTs

  16. Digital Logic Blocks with Tricks • How intelligent are current technologymappers when it comes to some commondigital logic blocks?

  17. a 00 b 01 out c 10 d 11 s1 s0 Techmap 4:1 MUX with 4-LUTs a b out c d s1 s0

  18. a 00 b 01 out c 10 d 11 s1 s0 Techmap 4:1 MUX with 4-LUTs a b s0 c out d s1

  19. a 00 b 01 out c 10 d 11 s1 s0 Techmap 4:1 MUX with 4-LUTs a s0 b s0 c out d s1=1

  20. Resuts using 4-LUTs

  21. Conclusions • Current 4-LUT technology mappers still have room for improvement(~5% on average, up to 10% for some circuits) • For some logic blocks, current technology mappers have a very difficult time finding the optimal mapping to 4-LUTs (~36% geomean, up to 67%). • Still has difficultly particularly for non-disjoint decomposition.

  22. Future Work • Explore BDDs, QBF solvers and All Solution SAT solvers to speed up process • If fast enough, this technique can be used asa valid resynthesis technique. • Use Multiple Output Resynthesis • Search for other optimal configurations ofcommon logic blocks, used in a caching schemefor resynthesis • After technology mapping, search for digital logic blocks found in our cache, replace digital logic block with the cached optimal configuration

  23. Questions?

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