Download
technology mapping of timed asynchronous circuits n.
Skip this Video
Loading SlideShow in 5 Seconds..
Technology Mapping of Timed Asynchronous Circuits PowerPoint Presentation
Download Presentation
Technology Mapping of Timed Asynchronous Circuits

Technology Mapping of Timed Asynchronous Circuits

193 Views Download Presentation
Download Presentation

Technology Mapping of Timed Asynchronous Circuits

- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. Technology Mapping of Timed Asynchronous Circuits Curtis A. Nelson University of Utah August 26, 2004

  2. Technology Mapping • Process of implementing a synthesized design. • Utilizes technology-specific libraries. • Combines the steps of: • Partitioning • Decomposition • Matching • Covering

  3. Specifications Technology Logic Synthesis Mapping Partitioning Cost Factors Decomposition Matching/Covering Library Physical Design Layout Synchronous Design Flow

  4. Specifications Technology Logic Synthesis Mapping Partitioning Cost Factors Decomposition Matching/Covering Library Physical Design Layout Asynchronous Design Flow Hazard Verification

  5. Timed Asynchronous Circuits • Timed circuits are a class of asynchronous circuits that use explicit timing information. • Can potentially reduce required circuitry as compared with speed-independent circuits. • Used in Intel RAPPID design which was 3 times faster than synchronous design. • As in all asynchronous circuits, timed circuit design is complicated by hazards.

  6. Hazards • Conditions that may manifest as glitches. • Caused by structure or timing of the circuit. • May result in incorrect behavior. • Must be detected and eliminated. • Two types of hazards: • Acknowledgment. • Monotonicity.

  7. Acknowledgement Hazard • Occurs when inputs to a gate change evaluation before the output stabilizes. 3 [2,4] 1 0 1 0 0

  8. Acknowledgement Hazard • Occurs when inputs to a gate change evaluation before the output stabilizes. [2,4] 0 1 0 1

  9. Acknowledgement Hazard • Occurs when inputs to a gate change evaluation before the output stabilizes. [2,4] 0 1 1

  10. Monotonicity Hazard • Occurs when an internal or output node: • Becomes excited to change when it should stay stable, or • Makes a transition non-monotonically. [4,6] 1 0 1 0 [1,3]

  11. Monotonicity Hazard • Occurs when an internal or output node: • Becomes excited to change when it should stay stable, or • Makes a transition non-monotonically. [4,6] 0 1 1 [1,3]

  12. Specifications Technology Logic Synthesis Mapping Partitioning Hazard Cost Factors Verification Decomposition Matching/Covering Library Physical Design Layout Asynchronous Design Flow

  13. Hazard Verification • Must check all reachable states for hazards. • Size of state space is O(2|I| x 2|O| x 2|N|). • Beerel/Burch/Meng proposed using a cube to approximate internal signal behavior for speed-independent circuits. • Reduces size of state space to O(2|I| x 2|O|). • We extend this application to timed circuits.

  14. Hazard Verification Algorithm • Input: Time Petri Net and Gate Netlist. • Check complex gate equivalence. • Determine stability of internal signals. • Check for acknowledgement hazards. • Check for monotonicity hazards.

  15. b+ [2,5] a+ [2,5] c- [2,5] d+ b+ [2,5] c+ [2,5] c+ [2,5] b- [2,5] a- [2,5] d- Time Petri Net • Specification method for timed systems. • Used to specify: • Environmental behavior. • Expected output behavior.

  16. b+ [2,5] a+ [2,5] c- [2,5] d+ b+ [2,5] c+ [2,5] c+ [2,5] b- [2,5] a- [2,5] d- Time Petri Net • State is a marking of places and ages of transitions. • Transition enabled when all input places are marked. • Transition fires after it has been enabled between [min,max] time units.

  17. Time Petri Net • After transition fires, marking removed from input places and added to output places. b+ [2,5] a+ [2,5] c- [2,5] d+ b+ [2,5] c+ [2,5] c+ [2,5] b- [2,5] a- [2,5] d-

  18. Gate Netlist [2,3] a [2,3] e d b c Gate-Level Netlist

  19. [2,6] a b d c Complex Gate Equivalent (CGE) Gate Netlist [2,3] a [2,3] e d b c Gate-Level Netlist

  20. b+ [2,5] a+ [2,5] [2,6] a c- [2,5] d+ b+ [2,5] b d c c+ [2,5] c+ [2,5] b- [2,5] a- [2,5] d- Checking Equivalence 0000 0000 abcd

  21. [2,6] a b d c Checking Equivalence b+ [2,5] a+ [2,5] 0000 0000 a+ c- [2,5] d+ b+ [2,5] 1000 1000 c+ [2,5] c+ [2,5] b- [2,5] a- [2,5] d- abcd abcd

  22. Checking Equivalence b+ [2,5] a+ [2,5] 0000 0000 a+ c- [2,5] d+ b+ [2,5] 1000 1000 b+ c+ [2,5] c+ [2,5] b- [2,5] 1100 1100 a- [2,5] d- [2,6] a b d abcd abcd c

  23. [2,6] a b d c Checking Equivalence b+ [2,5] a+ [2,5] 0000 0000 a+ c- [2,5] d+ b+ [2,5] 1000 1000 b+ c+ [2,5] c+ [2,5] b- [2,5] 1100 1100 d+ a- [2,5] d- 1101 1101 abcd abcd

  24. Checking Equivalence b+ [2,5] a+ [2,5] 0000 0000 a+ c- [2,5] d+ b+ [2,5] 1000 1000 b+ c+ [2,5] c+ [2,5] b- [2,5] 1100 1100 d+ a- [2,5] d- 1101 1101 [2,6] c+ c+ 1111 a 1111 b d abcd abcd c

  25. Checking Equivalence b+ [2,5] a+ [2,5] 0000 0000 a+ c- [2,5] d+ b+ [2,5] 1000 1000 b+ c+ [2,5] c+ [2,5] b- [2,5] 1100 1100 d+ a- [2,5] d- 1101 1110 1110 1101 [2,6] c+ c+ - d 1111 a 1111 b d abcd abcd c

  26. a - Checking Equivalence b+ [2,5] a+ [2,5] 0000 0000 a+ c- [2,5] d+ b+ [2,5] 1000 1000 b+ c+ [2,5] c+ [2,5] b- [2,5] 0110 1100 0110 1100 d+ a- [2,5] d- 1101 1110 1110 1101 [2,6] c+ c+ - d 1111 a 1111 b d abcd abcd c

  27. b+ [2,5] a+ [2,5] c- [2,5] d+ b+ [2,5] c+ [2,5] c+ [2,5] b- [2,5] - b a - a- [2,5] d- Checking Equivalence 0000 0000 a+ 1000 1000 b+ 0010 0010 0110 1100 0110 1100 d+ 1101 1110 1110 1101 [2,6] c+ c+ - d 1111 a 1111 b d abcd abcd c

  28. b+ [2,5] a+ [2,5] c- [2,5] d+ b+ [2,5] - b c+ [2,5] c+ [2,5] b- [2,5] a - a- [2,5] d- Checking Equivalence 0000 0000 a+ - c 1000 1000 b+ 0010 0010 0110 1100 0110 1100 d+ 1101 1110 1110 1101 [2,6] c+ c+ - d 1111 a 1111 b d abcd abcd c

  29. - b a - [2,6] a b d c Checking Equivalence b+ [2,5] a+ [2,5] 0000 0000 b+ a+ c- [2,5] d+ b+ [2,5] - 0100 c 1000 0100 1000 c+ b+ 0010 0010 c+ [2,5] c+ [2,5] b- [2,5] 0110 1100 0110 1100 d+ a- [2,5] d- 1101 1110 1110 1101 c+ c+ - d 1111 1111 abcd abcd

  30. b+ a+ 0000 c 0100 1000 b+ c+ 0010 0110 1100 b d+ a 1110 1101 c+ d 1111 abcd Finding Stable States a e d c b

  31. Finding Stable States b+ b+ a+ 0000 0000 a e c c 0100 0100 1000 d c b+ c+ c+ b 0010 0010 0110 1100 Step 1: Boolean evaluation of node e. b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  32. Finding Stable States b+ a+ 0000 a e c 0100 1000 d c b+ c+ b 0010 0110 1100 Step 2: Untimed stabilization of node e for d+ b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  33. Finding Stable States b+ a+ 0000 a e c 0100 1000 d c b+ c+ b 0010 0110 1100 Step 2: Untimed stabilization of node e for d+ b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  34. Finding Stable States b+ a+ 0000 a e c 0100 1000 d c b+ c+ b 0010 0110 1100 Step 2: State 1101 stable high. b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  35. Finding Stable States b+ a+ 0000 a e c 0100 1000 d c b+ c+ b 0010 0110 1100 Step 3: Untimed stabilization of node e for d- b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  36. Finding Stable States b+ a+ 0000 a e c 0100 1000 d c b+ c+ b 0010 0110 1100 Step 3: Untimed stabilization of node e for d- b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  37. Finding Stable States b+ a+ 0000 a e c 0100 1000 d c b+ c+ b 0010 0110 1100 Step 4: Propagate stable states. b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  38. a e d c b Finding Stable States b+ a+ 0000 c 0100 1000 b+ c+ 0010 0110 1100 Step 4: Propagate stable states. b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  39. a e d c b Checking for Hazards b+ a+ 0000 c 0100 1000 b+ c+ 0010 Node e is hazard-free! 0110 1100 b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  40. a a e e d c b d b c Alternative Gate-Level Netlist Try a different decomposition – Replace: With:

  41. Finding Stable States b+ a+ 0000 a e c 0100 1000 d b b+ c+ c 0010 0110 1100 Step 1: Boolean evaluation of node e. b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  42. Finding Stable States b+ a+ 0000 a e c 0100 1000 d b b+ c+ c 0010 0110 1100 Step 2: Untimed stabilization of node e for d+ b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  43. Finding Stable States b+ a+ 0000 a e c 0100 1000 d b b+ c+ c 0010 0110 1100 Step 2: Untimed stabilization of node e for d+ b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  44. Finding Stable States b+ a+ 0000 a e c 0100 1000 d b b+ c+ c 0010 0110 1100 Step 3: Propagate stable states. b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  45. Finding Stable States b+ a+ 0000 a e c 0100 1000 d b b+ c+ c 0010 0110 1100 Step 3: Propagate stable states. b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  46. Finding Stable States b+ a+ 0000 a e c 0100 1000 d b b+ c+ c 0010 0110 1100 Step 4: Untimed stabilization of node e for d- b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  47. Checking Acknowledgement b+ a+ 0000 a e c 0100 1000 d b b+ c+ c 0010 0110 1100 Node e may glitch. b d+ ACKNOWLEDGEMENT HAZARD! a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  48. Checking Monotonicity MONOTONICTY HAZARD! b+ a+ 0000 a e c 0100 1000 d b b+ c+ c 0010 0110 1100 Output d may glitch. b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  49. [2,3] [2,3] a e d b c Timed Stabilization b+ a+ 0000 c 0100 1000 b+ c+ 0010 0110 1100 Consider Netlist timing. b d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd

  50. [2,3] [2,3] a e d b c Timed Stabilization b+ a+ 0000 c 0100 1000 b+ c+ 0010 0110 1100 Minimum elapsed time: 2 b [2,5] d+ a 1110 1101 Rising High Falling Low c+ d 1111 abcd