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Register and Counter Design. Registers in the Basic Computer. Registers are basic building blocks in digital systems. store information auxiliary circuits may modify stored information or “steer it” to and from register. Registers and Counters.

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Register and Counter Design


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    1. Register and Counter Design

    2. Registers in the Basic Computer • Registers are basic building blocks in digital systems. • store information • auxiliary circuits may modify stored information or “steer it” to and from register

    3. Registers and Counters A register is a set of flip flops, often supplemented by additional circuits to control input and output. - can have parallel I/O or serial I/O or combination Usually, registers are used to store a set of related bits. -bits that collectively represent an integer value - bits of an ASCII character code -status bits for a device in a computer system (disk controller)‏ Counters are registers that store numeric values alongwith circuits to increment/decrement the stored value.

    4. counters - up-counters, down-counters, up-down counters - generalized counters - BCD counters, gray-code counters, ...

    5. Simple Parallel Load Register Four bit register » if LD is high when clock rises, new values are stored » LD should change only while CLK is high Registers using gated clocks • can lead to timing problems. • increases clock skew • may lead to violations of flip-flop setup, hold time specs • extra care needed to ensure correct operation • safer to avoid clock gating whenever possible

    6. Preferred Parallel Load Register Multiplexer for each register bit. » new value loaded when LD is lowotherwise, old value stored, No gated clock, - minimizing clock skew. » simplifies checking of setup and hold time specs. » can focus on delays between connected flip flops Increases gate count by about 30%.

    7. 4-bit Shift Register

    8. 2-bit Register

    9. Serial-in-serial-out Shift Register

    10. Design of SR FF library ieee; use ieee.std_logic_1164.all; entity ff is port ( s,r : in std_logic; q,qbar : out std_logic ); end ff; architecture behave of ff is begin process begin if (s = '0' and r = '0') then q <= '1'; qbar <= '0'; elsif (s = '0' and r = '1') then q <= '0'; qbar <= '1';

    11. SR FF (cont..)‏ elsif (s = '1' and r = '0') then q <= '1'; qbar <= '0'; else q <= '0'; qbar <= '0'; end if; end process; end behave;

    12. D-flip flop library ieee; use ieee.std_logic_1164.all; entity dff is port (d, clk : in std_logic; q, qbar : out std_logic ); end dff;

    13. architecture behave of dff is • signal temp : std_logic; • begin • process (clk)‏ • begin • if (clk'event and clk = '0') then • temp <= d; • end if; • q <= temp; • qbar <= not temp; • end process; • end behave;

    14. SR flip-flop (process)‏ library ieee; use ieee.std_logic_1164.all; entity ffclk is port ( s,r,clk : in std_logic; q,qbar : out std_logic ); end ffclk;

    15. architecture behave of ffclk is • signal temp,tempbar : std_logic; • begin • process (clk)‏ • begin • if (clk = '1') then • if (s = '0' and r = '0') then • temp <= '1'; • tempbar <= '0'; • elsif (s = '0' and r = '1') then • temp <= '0'; • tempbar <= '1';

    16. elsif (s = '1' and r = '0') then • temp <= '1'; • tempbar <= '0'; • else • temp <= '0'; • tempbar <= '0'; • end if; • else • temp <= temp; • tempbar <= tempbar; • end if; • q <= temp; • qbar <= tempbar; • end process; • --q <= temp; • --qbar <= tempbar; • end behave;

    17. counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity counter4bit is port (load,clear, clk : in std_logic; d : in std_logic_vector (3 downto 0); q : out std_logic_vector (3 downto 0)‏ ); end counter4bit;

    18. architecture behave of counter4bit is • signal temp : std_logic_vector (3 downto 0); • begin • a: process (clk,load,clear,d)‏ • begin • if (load = '1') then • temp <= d; • elsif (clear = '1') then • temp <= "0000"; • elsif (clk'event and clk = '1') then • temp <= temp + "0001"; • else

    19. temp <= temp; • end if; • end process a; • q <= temp; • --b: process (clk)‏ • --begin • --if (clk'event and clk = '1') then • --q <= temp; • --end if; • --end process b; • end behave;

    20. With second process (b)‏

    21. Serial-in-parallel-out Shift Register

    22. Synchronous Counter

    23. Ring Counter

    24. Up/down counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; -- up/down counter entity counterupdown is port (load,reset, clk : in std_logic; -- control signal dir : in std_logic; -- direction d : in std_logic_vector (3 downto 0); q : out std_logic_vector (3 downto 0)‏ ); end counterupdown;

    25. architecture behave of counterupdown is • begin • a: process (clk,reset,d)‏ • variable temp: std_logic_vector (3 downto 0); • begin • if (clk'event and clk = '1') then • if (reset = '1') then • temp := "0000"; • elsif (load = '0') then • temp := d; • else • if (dir = '1') then • temp := temp + "0001"; • else temp := temp - "0001"; • end if; end if; • end if; q <= temp; • end process a; end behave;

    26. Waveform (up/down counter)‏

    27. Binary counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity binarycounter is port (clk : in std_logic; q : out std_logic_vector (3 downto 0)‏ ); end binarycounter;

    28. architecture behave of binarycounter is • signal temp : std_logic_vector (3 downto 0); • begin • a: process (clk)‏ • begin • if (clk'event and clk = '0') then • temp <= temp + "0001"; • end if; • q <= temp; • end process a; • end behave;

    29. Waveform (binary counter)‏

    30. Mod 2 counter library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; use ieee.std_logic_arith.all; entity mod2 is port (clk : in std_logic; q : out std_logic_vector (3 downto 0)‏ ); end mod2;

    31. architecture behave of mod2 is • signal temp : std_logic_vector (3 downto 0); • begin • a: process (clk)‏ • begin • if (clk'event and clk = '0') then • if (temp = "0010" ) then • temp <= "0000"; • else • temp <= temp + "0001"; • end if; • end if; • q <= temp; • end process a; • end behave;

    32. Waveform (mod 2 counter)‏