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  1. IEG4020 Telecommunication Switching and Network Systems Chapter 3 Fundamental Principles of Packet Switch Design

  2. Output destinations are random … 4x4 Switch 3 1 1 1 … 4 2 4 2 … 1 1 3 … 4 2 4 Idle slots (no active packets) Arrival boundaries may be unaligned Fig. 3.1. Packet arrivals in a 4 x 4 packet switch

  3. To Switch Input Info Disassembler Delay Assembler ( Output VCI ) Header Header Processor ( Input VCI ) Input VCI Output Address Output VCI Memory 1 5 2 2 12 5 . . . . . . Fig. 3.2. Input packet processor VCI: virtual-circuit identifier

  4. VCI of a virtual channel may change from link to link 2 2 3 2 2 2 • Simplify VCI assignment algorithm • Reduce blocking due to shortage of valid VCI

  5. Packet Contention in Switches Loss System : • No input or internal buffers. Packets may need to queue at outputs if group size is greater than 1 • Packets may be dropped internally or at outputs due to contention. Loss probability can be made arbitrarily small Waiting System : • Contention Resolution mechanism to select packets to be switched • Losing packets buffered at inputs or internally • Output buffers needed if group size is greater than 1 • Throughput can be made arbitrarily close to 100%

  6. 4 x 4 1 1 1 2 1 3 2 4 Packets may be switched one by one to outputs if speedup is N times, not viable for large N Solutions for Packet Contention Fig. 3.3. (a) Speeding up switch operation by N times 1) Speeding up packet switching Speedup factor ≥ 3  solve the contention problem in this example

  7. 4 x 4 1 1 One of these packets must be dropped if group size = 2 1 2 1 3 2 4 Solutions for Packet Contention Fig. 3.3. (b) Dropping packets that cannot be switched 2) Discard Packets

  8. 4 x 4 1 1 Two of these packets must be buffered if group size = 1 1 2 1 3 2 4 Solutions for Packet Contention Fig. 3.3. (c) Queueing packets that cannot be switched 3) BufferPackets

  9. Fundamental properties of interconnection networks Interconnection Networks : • Originally intended for multiprocessor computer interconnect • distributed, self-routing algorithms • regular topological interconnection pattern Rearrangeable nonblocking in circuit switching is the same as internally nonblocking in packet switching Speed is the practical difference !

  10. * Definition: Not internally nonblocking * Unique path from input to output * log2N stages Networks (a) and (c) are isomorphic: one can be obtained from the other by interchanging the shaded elements Banyan Networks Fig. 3.4. (a) shuffle-exchange (omega) network; (b) reverse shuffle- exchange network; (c) banyan network; (d) baseline network

  11. 000 100 100 101 100 101 101 0 1 0 1 0 1 001 010 0 1 0 1 0 1 011 100 0 1 0 1 0 1 101 110 0 1 0 1 0 1 111 Destination addresses are in binary form. The log2N-bit address is used as the routing bits for the packet: bit i is used in stagei Banyan Network Fig. 3.5. Routing in the banyan network

  12. One packet must be dropped 000 000 100 000 000 100 External Conflict 000 0 1 0 1 0 1 001 010 0 1 0 1 0 1 011 100 0 1 0 1 0 1 101 110 0 1 0 1 0 1 111 Internal Conflict Fig. 3.6. Internal and external conflicts when routing packets in a banyan network

  13. Loss probability in a Banyan Network :

  14. Pm Pm+1 m + 1 Ploss = n / (n+4) 0.6 0.5 0.4 λ = 1 0.3 0.2 0.1 n = log2N 1 2 3 4 5 6 7 Fig. 3.7. Loss probability of the Banyan network operating as a loss system

  15. Combinatoric Properties of Banyan Networks :

  16. Nonblocking Conditions for the Banyan Networks : Banyan network is nonblocking if active inputs x1, … xm, (xi, > xj, if j > 1) and their targeted outputs y1, … ym satisfy : 1.) Distinct and monotonic outputs: y1 < y2 < … < ym or ym > … > y2 > y1 2.) Concentrated inputs:

  17. 000 110 110 011 010 001 010 001 011 001 010 011 100 101 110 111 000 Sorting Network 001 010 011 100 101 110 111 Fig. 3.8. (b) Nonblocking sort-banyan network Fig. 3.8. (a) An example showing the banyan network is nonblocking for sorted inputs

  18. Subnetwork 0 Subnetwork 00 0000 0000 000,Φ 00,0 0,00 Φ, 000 0001 0001 0010 0010 001,Φ 01,0 1,00 Φ, 001 0011 0011 0100 0100 010,Φ 10,0 0,01 Φ, 010 0101 0101 0110 0110 011,Φ 11,0 1,01 Φ, 011 0111 0111 1000 1000 100,Φ 00,1 0,10 Φ, 100 1001 1001 1010 1010 101,Φ 01,1 1,10 Φ, 101 1011 1011 1100 1100 110,Φ 10,1 0,11 Φ, 110 1101 1101 1110 1110 111,Φ 11,1 1,11 Φ, 111 1111 1111 Subnetwork 1 Fig. 3.9. (a) Labeling of nodes in the banyan network

  19. Stage-1 Node Stage-2 Node Stage-n Node … Input Output … b1 bn an …a1 (an-1 …a1 ,Φ) (an-2 …a1 ,b1) (Φ, b1 …bn-1) (b1 …bn) Banyan Network – Routing Algorithm Fig. 3.9. (b) Sequence of nodes traversed by a packet from input an … a1 to output bn… b1

  20. 0 (an-2 …a1 ,0) … 0 Stage-1 Node Stage-2 Node Stage-3 Node 1 … an …a1 (an-1 …a1 ,Φ) Input 0 1 (an-2 …a1 ,1) … 1 Without collision, a packet with input an …a1 and output b1 …bn will be in node an-k …a1, b1 …bk-1 at stage k Stage k : an-k …a1, b1 …bk-1 Banyan Network – Routing Algorithm

  21. y’ x x’ y . . . . . . . . . . . . Banyan Network – SNB Proof Proof :Two packets: 1st packet : x = an…a1 y = b1…bn 2nd packet : x’ = an’…a1’y’ = b1’…bn’ collide in stage k

  22. y x x’ y’ . . . . Banyan Network – SNB Proof But if conditions are satisfied : 1.) There are | x’ – x + 1 | active inputs between x’ and x They must have distinct outputs 2.) | y’ – y + 1 | >= number of distinct outputs = | x’ – x + 1 | i.e. | y’ – y | >= | x’ – x |

  23. 111 000 110 010 101 001 011 100 000 001 010 011 100 101 110 111 Banyan Network with sorted input packets Fig. 3.10. An example of unsorted packets having no conflict in the banyan network

  24. 110 011 010 001 000 001 010 011 100 101 110 111 (x1, y1) (x1 + Z mod N, y1) . . nonblocking . . (xm, ym) (xm+ Z mod N, ym) Fig. 3.11. Sorted packets remains unblocked after their inputs are shifted (mod 8) by 6

  25. RBN RBN (shifted concentration) Concentration : Routing: bits are used starting from L.S.B to M.S.B.

  26. 3 1 4 2 1 3 2 4 4 1 4 1 1 1 2 1 3 2 1 3 Fig. 3.12. (a) Sorting network switches correctly when all inputs are active and have no common outputs Fig. 3.12. (b) Sorting network switches incorrectly when some inputs are inactive Fig. 3.12. (c) Sorting network switches incorrectly when some inputs have common outputs

  27. real packets Sorting Network 4 1 2 2 1 3 3 4 dummy packets discarded at outputs dummy packets with destinations chosen to be nonconflicting Sorting Network Fig 3.13. An example showing that dummy packets with nonconflicting destinations may be introduced to make the sorting network switch correctly when not all inputs are active, this requires knowledge of the destinations of active inputs

  28. ai min(ai, aj) aj max(ai, aj) ai min(ai, aj) aj max(ai, aj) Comparator Fig. 3.14. (a) A comparator Fig. 3.14. (b) A compact way of representing a comparator

  29. a1 b1 a2 b2 a3 b3 a4 b4 stage 1 stage 2 stage 3 a1 b1 a2 b2 a3 b3 a4 b4 Structure of Sorting Network Fig. 3.15. (a) A 4x4 sorting network -- Compact representation Fig. 3.15. (b) A 4x4 sorting network -- Full representation

  30. Comparison Networks Order-preserving property Sorting Networks 0-1 principle Sorting Network vs Comparison Network

  31. Example : f(.) 2 3 1 2 + 3 4 4 2 3 3 1 3 2 2 1 2 3 4 Order-preserving Property : Suppose a comparison network maps input sequence a = < a1, …, aN > to output sequence b = < b1, …, bN >, Then for any monotonically increasing function f(.), it maps f(a) = < f(a1), …, f(aN) > to f(b) = < f(b1), …, f(bN) > ( Basic idea: large numbers remain larger (no smaller) than small numbers after mapping → Comparator states do not change)

  32. min(x, y) x y max(x, y) min(f(x), f(y)) f(x) f(y) max(f(x), f(y)) Fig. 3.16. Illustration that a comparator has the order-preserving property

  33. ai ci = min(ai, aj) aj cj = max(ai, aj) min(f(ai), f(aj)) = f(min(ai, aj) ) = f(cj) f(ai) f(aj) f(cj) Output of stages before stage d By assumption of induction, they must be f(ai) and f(aj) Fig. 3.17. (a) The inputs and outputs of a comparator at stage d when input sequence is a Fig. 3.17. (b) The inputs and outputs of the same comparator when input sequence is f(a)

  34. By contradiction, assume ai< aj, but aj placed before ai aj Sorting Network Sorting Network < a1, …, aN > ai By order-preserving property f(aj) = 1 . . . . < f(a1), …, f(aN) > (zero-one sequence) . . . . . . f(ai) = 0 . . . . 1 x 0 ai Fig. 3.18. Illustration of the proof of the zero-one principle

  35. 2-merger 4-merger N/2-merger N-merger 2-merger … 2-merger 4-merger N/2-merger 2-merger N-merger k/2 sorted numbers k sorted numbers . . . . . . . . . . . . . . . . k/2 sorted numbers . . 2-merger = comparator Fig. 3.19. Sorting based on merging, successive shorter sorted sequences are merged into longer sorted sequences

  36. 0 0 0 0 2 - m 4 - m 8 - m 1 1 0 0 0 1 1 0 2 - m 1 0 1 0 0 0 0 1 2 - m 4 - m 1 1 0 1 0 0 1 1 2 - m 1 1 1 1 Example of sorting by merger :

  37. Ascending Sequence k-bitonic sorter k-bitonic sorter Ascending Sequence Descending Sequence . . . . . . . . . . . . . . . . . . Descending Sequence Ascending Sequence Ascending Sequence Fig. 3.20. Bitonic Sorters or The two input sequences do not have to be the same length The two input sequences are of opposing directions

  38. a1 min(a1, an+1) a2 min(a2, an+2) a’ bitonic an min(an, a2n) an+1 max(a1, an+1) an+2 a” bitonic max(a2, an+2) a2n max(an, a2n) . . . . . . . . . . . . If a is a zero-one sequence, either a’ is all 0’s or a” is all 1’s, or both Half-cleaner Fig. 3.21. A half-cleaner

  39. Compare 0 0 Bitonic Clean 0 0 1 1 0 0 1 1 Bitonic Top Bottom Min Max 0 0 Compare 0 0 0 Bitonic Clean 1 0 0 0 0 1 1 Bitonic 1 Top Bottom Min Max Half-cleaner - operations Fig. 3.22. Operations performed by a half-cleaner for different cases

  40. Compare 0 0 0 Bitonic Clean 0 0 0 1 0 Bitonic 0 Top Bottom Min Max Compare 0 0 0 Bitonic 1 0 1 0 1 0 1 1 Bitonic Clean 0 0 Top Bottom Min Max Half-cleaner - operations Fig. 3.22. Operations performed by a half-cleaner for different cases

  41. Examples of Bitonic Sequence (Circularly Bitonic) :

  42. Half of #s above green line, half below Min Max Physical picture of half-cleaner action on arbitrary-number bitonic sequence :

  43. k/2-bitonic cleaner k-half cleaner k/2-bitonic cleaner . . . . . . . . . . . . . . . Bitonic Sorter Fig. 3.23. Recursive construction of a k-bitonic sorter (merger)

  44. 4-bitonic sorter 4-bitonic sorter 8-bitonic sorter 2-bitonic sorter 2-bitonic sorter 2-bitonic sorter 2-bitonic sorter Four 2-bitonic sorter Two 4-bitonic sorter One 8-bitonic sorter Bitonic Sorting Network Fig. 3.24. (a) A sorting network based on merging using bitonic sorters Fig. 3.24. (b) The same network broken down into comparators

  45. a1 d1 c1 Odd Merge a2 d2 c2 a3 d3 c3 a4 d4 c4 c5 c6 an dn c7 . . . . . . . . . . . . . . . . . . b1 e1 Even Merge b2 e2 b3 e3 b4 e4 bn en c2n Odd-even Sorting Network Fig. 3.25 Recursion for Odd-even Sorting Network

  46. Odd-even Sorting Network - Proof

  47. Odd-even Sorting Network - Proof

  48. Odd-even Sorting Network - Proof

  49. Odd-even Sorting Network - Proof

  50. Information bits 00 01 Remain in bar state after second bit … … 0100 Comparator in bar state 10 00 … 1000 … Order of arrival from right to left Set to cross state after third bit because upper input is larger, remains in cress state for the whole packet duration 000 0 Header … … 0 1 100 010 Remain in bar state after first bit … 100 0 Fig. 3.26. The operation of a comparator used in a sorting network for packet switching