chapter 3 n.
Download
Skip this Video
Loading SlideShow in 5 Seconds..
Chapter 3 PowerPoint Presentation
Download Presentation
Chapter 3

Loading in 2 Seconds...

play fullscreen
1 / 86

Chapter 3 - PowerPoint PPT Presentation


  • 64 Views
  • Uploaded on

IEG4020 Telecommunication Switching and Network Systems. Chapter 3. Fundamental Principles of Packet Switch Design. Output destinations are random. …. 4 x4 Switch. 3. 1. 1. 1. …. 4. 2. 4. 2. …. 1. 1. 3. …. 4. 2. 4. Idle slots (no active packets).

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Chapter 3' - rod


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
chapter 3

IEG4020

Telecommunication Switching and Network Systems

Chapter 3

Fundamental Principles of Packet Switch Design

fig 3 1 packet arrivals in a 4 x 4 packet switch

Output destinations are random

4x4

Switch

3

1

1

1

4

2

4

2

1

1

3

4

2

4

Idle slots

(no active packets)

Arrival boundaries may be unaligned

Fig. 3.1. Packet arrivals in a 4 x 4 packet switch
fig 3 2 input packet processor

To Switch

Input

Info

Disassembler

Delay

Assembler

( Output VCI )

Header

Header

Processor

( Input VCI )

Input

VCI

Output

Address

Output

VCI

Memory

1

5

2

2

12

5

.

.

.

.

.

.

Fig. 3.2. Input packet processor

VCI: virtual-circuit identifier

slide4

VCI of a virtual channel may change from link to link

2

2

3

2

2

2

  • Simplify VCI assignment algorithm
  • Reduce blocking due to shortage of valid VCI
slide5

Packet Contention in Switches

Loss System :

  • No input or internal buffers. Packets may need to queue at outputs if group size is greater than 1
  • Packets may be dropped internally or at outputs due to contention. Loss probability can be made arbitrarily small

Waiting System :

  • Contention Resolution mechanism to select packets to be switched
  • Losing packets buffered at inputs or internally
  • Output buffers needed if group size is greater than 1
  • Throughput can be made arbitrarily close to 100%
fig 3 3 a speeding up switch operation by n times

4 x 4

1

1

1

2

1

3

2

4

Packets may be switched one by one to outputs if speedup is N times, not viable for large N

Solutions for Packet Contention

Fig. 3.3. (a) Speeding up switch operation by N times

1) Speeding up packet switching

Speedup factor ≥ 3

 solve the contention problem in this example

fig 3 3 b dropping packets that cannot be switched

4 x 4

1

1

One of these

packets must

be dropped if

group size = 2

1

2

1

3

2

4

Solutions for Packet Contention

Fig. 3.3. (b) Dropping packets that cannot be switched

2) Discard Packets

fig 3 3 c queueing packets that cannot be switched

4 x 4

1

1

Two of these

packets must

be buffered if

group size = 1

1

2

1

3

2

4

Solutions for Packet Contention

Fig. 3.3. (c) Queueing packets that cannot be switched

3) BufferPackets

slide9

Fundamental properties of interconnection networks

Interconnection Networks :

  • Originally intended for multiprocessor computer interconnect
  • distributed, self-routing algorithms
  • regular topological interconnection pattern

Rearrangeable nonblocking in circuit switching is the

same as internally nonblocking in packet switching

Speed is the practical difference !

slide10

* Definition:

Not internally

nonblocking

* Unique path

from input

to output

* log2N stages

Networks (a) and (c) are isomorphic: one can be obtained from the other by interchanging the shaded elements

Banyan Networks

Fig. 3.4. (a) shuffle-exchange (omega) network; (b) reverse shuffle- exchange network; (c) banyan network; (d) baseline network
fig 3 5 routing in the banyan network

000

100

100

101

100

101

101

0

1

0

1

0

1

001

010

0

1

0

1

0

1

011

100

0

1

0

1

0

1

101

110

0

1

0

1

0

1

111

Destination addresses are in binary form. The log2N-bit address is used as the routing bits for the packet: bit i is used in stagei

Banyan Network

Fig. 3.5. Routing in the banyan network
fig 3 6 internal and external conflicts when routing packets in a banyan network

One packet must be dropped

000

000

100

000

000

100

External Conflict

000

0

1

0

1

0

1

001

010

0

1

0

1

0

1

011

100

0

1

0

1

0

1

101

110

0

1

0

1

0

1

111

Internal Conflict

Fig. 3.6. Internal and external conflicts when routing packets in a banyan network
fig 3 7 loss probability of the banyan network operating as a loss system

Pm

Pm+1

m + 1

Ploss = n / (n+4)

0.6

0.5

0.4

λ = 1

0.3

0.2

0.1

n = log2N

1

2

3

4

5

6

7

Fig. 3.7. Loss probability of the Banyan network operating as a loss system
slide16

Nonblocking Conditions for the Banyan Networks :

Banyan network is nonblocking if active inputs

x1, … xm, (xi, > xj, if j > 1) and their targeted outputs

y1, … ym satisfy :

1.) Distinct and monotonic outputs:

y1 < y2 < … < ym or ym > … > y2 > y1

2.) Concentrated inputs:

slide17

000

110

110

011

010

001

010

001

011

001

010

011

100

101

110

111

000

Sorting

Network

001

010

011

100

101

110

111

Fig. 3.8. (b) Nonblocking sort-banyan network

Fig. 3.8. (a) An example showing the banyan network is

nonblocking for sorted inputs

fig 3 9 a labeling of nodes in the banyan network

Subnetwork 0

Subnetwork 00

0000

0000

000,Φ

00,0

0,00

Φ, 000

0001

0001

0010

0010

001,Φ

01,0

1,00

Φ, 001

0011

0011

0100

0100

010,Φ

10,0

0,01

Φ, 010

0101

0101

0110

0110

011,Φ

11,0

1,01

Φ, 011

0111

0111

1000

1000

100,Φ

00,1

0,10

Φ, 100

1001

1001

1010

1010

101,Φ

01,1

1,10

Φ, 101

1011

1011

1100

1100

110,Φ

10,1

0,11

Φ, 110

1101

1101

1110

1110

111,Φ

11,1

1,11

Φ, 111

1111

1111

Subnetwork 1

Fig. 3.9. (a) Labeling of nodes in the banyan network
fig 3 9 b sequence of nodes traversed by a packet from input a n a 1 to output b n b 1

Stage-1 Node

Stage-2 Node

Stage-n Node

Input

Output

b1

bn

an …a1

(an-1 …a1 ,Φ)

(an-2 …a1 ,b1)

(Φ, b1 …bn-1)

(b1 …bn)

Banyan Network – Routing Algorithm

Fig. 3.9. (b) Sequence of nodes traversed by a packet from input an … a1 to output bn… b1
slide20

0

(an-2 …a1 ,0)

0

Stage-1 Node

Stage-2 Node

Stage-3 Node

1

an …a1

(an-1 …a1 ,Φ)

Input

0

1

(an-2 …a1 ,1)

1

Without collision, a packet with input an …a1 and output b1 …bn will be in node an-k …a1, b1 …bk-1 at stage k

Stage k :

an-k …a1,

b1 …bk-1

Banyan Network – Routing Algorithm

slide21

y’

x

x’

y

.

.

.

.

.

.

.

.

.

.

.

.

Banyan Network – SNB Proof

Proof :Two packets:

1st packet : x = an…a1 y = b1…bn

2nd packet : x’ = an’…a1’y’ = b1’…bn’

collide in stage k

slide22

y

x

x’

y’

.

.

.

.

Banyan Network – SNB Proof

But if conditions are satisfied :

1.) There are | x’ – x + 1 | active inputs

between x’ and x

They must have distinct outputs

2.) | y’ – y + 1 | >= number of distinct outputs

= | x’ – x + 1 |

i.e. | y’ – y | >= | x’ – x |

fig 3 10 an example of unsorted packets having no conflict in the banyan network

111

000

110

010

101

001

011

100

000

001

010

011

100

101

110

111

Banyan Network with sorted input packets

Fig. 3.10. An example of unsorted packets having no conflict in the banyan network
fig 3 11 sorted packets remains unblocked after their inputs are shifted mod 8 by 6

110

011

010

001

000

001

010

011

100

101

110

111

(x1, y1)

(x1 + Z mod N, y1)

.

.

nonblocking

.

.

(xm, ym)

(xm+ Z mod N, ym)

Fig. 3.11. Sorted packets remains unblocked after their inputs are shifted (mod 8) by 6
slide25

RBN

RBN

(shifted concentration)

Concentration :

Routing: bits are used starting from L.S.B to M.S.B.

slide26

3

1

4

2

1

3

2

4

4

1

4

1

1

1

2

1

3

2

1

3

Fig. 3.12. (a) Sorting network switches correctly when all inputs are active and have no

common outputs

Fig. 3.12. (b) Sorting network switches incorrectly when some inputs are inactive

Fig. 3.12. (c) Sorting network switches incorrectly when some inputs have common outputs

slide27

real packets

Sorting

Network

4

1

2

2

1

3

3

4

dummy packets discarded at outputs

dummy packets with destinations chosen to be nonconflicting

Sorting Network

Fig 3.13. An example showing that dummy packets with nonconflicting

destinations may be introduced to make the sorting network switch

correctly when not all inputs are active, this requires knowledge of the

destinations of active inputs

slide28

ai

min(ai, aj)

aj

max(ai, aj)

ai

min(ai, aj)

aj

max(ai, aj)

Comparator

Fig. 3.14. (a) A comparator

Fig. 3.14. (b) A compact way of representing a comparator

slide29

a1

b1

a2

b2

a3

b3

a4

b4

stage

1

stage

2

stage

3

a1

b1

a2

b2

a3

b3

a4

b4

Structure of Sorting Network

Fig. 3.15. (a) A 4x4 sorting network -- Compact representation

Fig. 3.15. (b) A 4x4 sorting network -- Full representation

slide30

Comparison

Networks

Order-preserving property

Sorting

Networks

0-1 principle

Sorting Network vs Comparison Network

slide31

Example :

f(.)

2

3

1

2

+

3

4

4

2

3

3

1

3

2

2

1

2

3

4

Order-preserving Property :

Suppose a comparison network maps input sequence

a = < a1, …, aN > to output sequence b = < b1, …, bN >,

Then for any monotonically increasing function f(.),

it maps f(a) = < f(a1), …, f(aN) > to f(b) = < f(b1), …, f(bN) >

( Basic idea: large numbers remain larger (no smaller) than small numbers after mapping

→ Comparator states do not change)

slide32

min(x, y)

x

y

max(x, y)

min(f(x), f(y))

f(x)

f(y)

max(f(x), f(y))

Fig. 3.16. Illustration that a comparator has the order-preserving property

slide33

ai

ci = min(ai, aj)

aj

cj = max(ai, aj)

min(f(ai), f(aj))

= f(min(ai, aj) ) = f(cj)

f(ai)

f(aj)

f(cj)

Output of stages before stage d

By assumption of induction, they must be f(ai) and f(aj)

Fig. 3.17. (a) The inputs and outputs of a comparator at stage d when input

sequence is a

Fig. 3.17. (b) The inputs and outputs of the same comparator when

input sequence is f(a)

fig 3 18 illustration of the proof of the zero one principle

By contradiction, assume ai< aj, but aj placed before ai

aj

Sorting

Network

Sorting

Network

< a1, …, aN >

ai

By order-preserving property

f(aj) = 1

.

.

.

.

< f(a1), …, f(aN) >

(zero-one sequence)

.

.

.

.

.

.

f(ai) = 0

.

.

.

.

1

x

0

ai

Fig. 3.18. Illustration of the proof of the zero-one principle
slide35

2-merger

4-merger

N/2-merger

N-merger

2-merger

2-merger

4-merger

N/2-merger

2-merger

N-merger

k/2 sorted numbers

k sorted numbers

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

k/2 sorted numbers

.

.

2-merger = comparator

Fig. 3.19. Sorting based on merging, successive shorter sorted sequences

are merged into longer sorted sequences

slide36

0

0

0

0

2 - m

4 - m

8 - m

1

1

0

0

0

1

1

0

2 - m

1

0

1

0

0

0

0

1

2 - m

4 - m

1

1

0

1

0

0

1

1

2 - m

1

1

1

1

Example of sorting by merger :

fig 3 20 bitonic sorters

Ascending Sequence

k-bitonic

sorter

k-bitonic

sorter

Ascending Sequence

Descending Sequence

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Descending Sequence

Ascending Sequence

Ascending Sequence

Fig. 3.20. Bitonic Sorters

or

The two input sequences do not have to be the same length

The two input sequences are of opposing directions

fig 3 21 a half cleaner

a1

min(a1, an+1)

a2

min(a2, an+2)

a’

bitonic

an

min(an, a2n)

an+1

max(a1, an+1)

an+2

a”

bitonic

max(a2, an+2)

a2n

max(an, a2n)

.

.

.

.

.

.

.

.

.

.

.

.

If a is a zero-one sequence, either a’ is all 0’s or a” is all 1’s, or both

Half-cleaner

Fig. 3.21. A half-cleaner
fig 3 22 operations performed by a half cleaner for different cases

Compare

0

0

Bitonic Clean

0

0

1

1

0

0

1

1

Bitonic

Top

Bottom

Min

Max

0

0

Compare

0

0

0

Bitonic Clean

1

0

0

0

0

1

1

Bitonic

1

Top

Bottom

Min

Max

Half-cleaner - operations

Fig. 3.22. Operations performed by a half-cleaner for different cases
fig 3 22 operations performed by a half cleaner for different cases1

Compare

0

0

0

Bitonic Clean

0

0

0

1

0

Bitonic

0

Top

Bottom

Min

Max

Compare

0

0

0

Bitonic

1

0

1

0

1

0

1

1

Bitonic Clean

0

0

Top

Bottom

Min

Max

Half-cleaner - operations

Fig. 3.22. Operations performed by a half-cleaner for different cases
slide42

Half of #s above green line, half below

Min

Max

Physical picture of half-cleaner action on arbitrary-number

bitonic sequence :

fig 3 23 recursive construction of a k bitonic sorter merger

k/2-bitonic

cleaner

k-half

cleaner

k/2-bitonic

cleaner

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

Bitonic Sorter

Fig. 3.23. Recursive construction of a k-bitonic sorter (merger)
slide44

4-bitonic

sorter

4-bitonic

sorter

8-bitonic

sorter

2-bitonic

sorter

2-bitonic

sorter

2-bitonic

sorter

2-bitonic

sorter

Four 2-bitonic sorter

Two 4-bitonic sorter

One 8-bitonic sorter

Bitonic Sorting Network

Fig. 3.24. (a) A sorting network based on merging using bitonic sorters

Fig. 3.24. (b) The same network broken down into comparators

fig 3 25 recursion for odd even sorting network

a1

d1

c1

Odd

Merge

a2

d2

c2

a3

d3

c3

a4

d4

c4

c5

c6

an

dn

c7

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

b1

e1

Even

Merge

b2

e2

b3

e3

b4

e4

bn

en

c2n

Odd-even Sorting Network

Fig. 3.25 Recursion for Odd-even Sorting Network
slide50

Information bits

00

01

Remain in bar state after second bit

0100

Comparator in bar state

10

00

1000

Order of arrival from right to left

Set to cross state after third bit because upper input is larger, remains in cress state for the whole packet duration

000

0

Header

0

1

100

010

Remain in bar state after first bit

100

0

Fig. 3.26. The operation of a comparator used in a sorting network

for packet switching

fig 3 27 an 8x8 batcher banyan network

Batcher (Bitonic Sort) Network

Banyan Network

010

011

000

0

1

0

1

0

1

001

011

010

0

1

0

1

0

1

011

010

100

0

1

0

1

0

1

101

110

0

1

0

1

0

1

111

Shuffle

MSB

1 if inactive

Activity

Bit

Address

Activity Bit

0 if active

Batcher-banyan network

Fig. 3.27. An 8x8 Batcher-banyan network
slide52

Batcher-banyan network - Complexity

Number of comparators in a Batcher bitonic sorting network :

* f(k) = # stages in a k-bitonic sorter

= log2k

fig 3 28 a three phase scheme for sort banyan network stage 1 probing for conflict

2

4

Banyan

Network

5

4

4

i

Output Destinations

i = idle outputs

4

4

5

i

2

i

i

4

i

i

Sorting Network

Sorted header. Each output examines the output above for possible conflict

Three-phase scheme – stage 1

Fig. 3.28. (a) Three-phase scheme for sort-banyan network ( Stage 1: probing for conflict )
fig 3 28 b three phase scheme for sort banyan network stage 2 acknowledgement of winning packets

2

Banyan

Network

4

4

4

5

i

i

i

Acknowledgement path is reverse of forward sorting path

Three-phase scheme – stage 2

Fig. 3.28. (b) Three-phase scheme for sort-banyan network ( Stage 2: acknowledgement of winning packets )
fig 3 28 c three phase scheme for sort banyan network stage 3 routing winning packets

Concentrated and monotonic output addresses

4

2

5

4

5

2

Three-phase scheme – stage 3

Fig. 3.28. (c) Three-phase scheme for sort-banyan network ( Stage 3: routing winning packets )
slide56

Nonblocking and Self-routing Properties of Clos Networks

Packet switching with Clos networks :

  • The Clos network — first studied by C. Clos in 1953
  • Features :

— Rearrangeably non-blocking

— Requires centralized route assignment

— Self-routing is impossible in genernal [1]

[1]B.G. Douglass and A.Y. Oruc, “On self-routing in Clos connection networks”, IEEE Trans. On Commun., Vol. 41, No. 1, Jan 1993, pp.121-124

slide57

Nonblocking Route Assignment

  • Generalization of the sort-banyan principle
  • The non-blocking and self-routing properties of Clos network
  • Simple route assignment with an appropriate addressing scheme
  • General Clos-type network from the cascade combination of a MIN and its reverse network
fig 3 30 a three stage clos network with address numbering scheme

q × q

s

[s]q

q × q

p × p

[d]q

d

0

0

0

0

0

0

0

0

0

0

0

1

1

1

1

q-1

q-1

q-1

p-1

p-1

q-1

q-1

q-1

q

0

0

0

0

0

0

q

1

1

1

q+1

1

1

q+1

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

.

2q-1

q-1

q-1

p-1

p-1

q-1

q-1

2q-1

(p-1)q

0

0

0

0

0

0

(p-1)q

p-1

q-1

p-1

(p-1)q+1

1

1

(p-1)q+1

pq-1

q-1

q-1

p-1

p-1

q-1

q-1

pq-1

Address Numbering Scheme

Fig. 3.30. A three-stage Clos network with address numbering scheme

a

b

slide59

b

q = 4

3

7

11

3

2

6

10

2

1

5

9

1

0

4

8

a

0

1

2

p = 3

d = aq+ b,

Continued:

slide60

Nonblocking Route Assignment

A sufficient non-blocking condition :

Let π= {(s1, d1), … , (sn, dn)}

An assignment f : π→ C is non-blocking if

slide61

A fundamental lemma :

Let x1, x2,…, xn be a strictly monotonic sequence of integers and for all i, define

g(xi) = [m+i]q for all i

where m and q are constant integers. Then

slide62

j - i

Proof :

Without loss of generality, assume that the sequence is increasing and let i < j. We have

slide63

Rank-based assignment algorithm :

Route assignment based on the “rank” of each connection request

Let π= {(s1, d1),…,(sn, dn)} be monotonic. The assignment

f (s1, d1) = [m + i]q

where m is a constant integer and i is the rank of connection (si, di) in π, is non-blocking [2]

[2] K. Sezaki, Y. Tanaka and M. Akiyama, “N:1 Connection Switching Networks Suited for Time Division Switching”, Computer Networks and ISDN Systems, No. 20, 1990, pp. 383-389

slide64

Proof :

The sequences (s1,…, sn) and (d1,…, dn) are monotonic

Let

g1(si) = f (si, π(si)) = f (si, di) = [m + i]q

g2(di) = f (π-1(di), di) = f (si, di) = [m + i]q

Thus f (si, di) = f (sj, dj) implies

g1(si) = g1(sj) and g2(di) = g2(dj)

Hence the assignment is non-blocking

fig 3 31 route assignment for

1 3 5 6 9 11

π=

2 4 7 9 10 11

si

1

3

5

6

9

11

di

2

4

7

9

10

11

m + i

0

1

2

3

4

5

f (si, di) = [m + i]q

0

1

2

3

0

1

Routing tag

(0,0,2)

(1,1,0)

(2,1,3)

(3,2,1)

(0,2,2)

(1,2,3)

0

0

(0,0)

1

1

(0,1)

2

2

(0,2)

(0,3)

3

3

4

4

(1,0)

5

5

(1,1)

6

6

(1,2)

(1,3)

7

7

8

8

(2,0)

9

9

(2,1)

10

10

(2,2)

(2,3)

11

11

Fig. 3.31. Route assignment for π

An example :

fig 3 32 order is preserved in a middle stage module m

si

mi

ni

M

di

.

.

.

.

.

.

.

.

si < sj

di < dj

.

.

.

.

mj

nj

sj

dj

Fig. 3.32. Order is preserved in a middle-stage module M

Order preserving property :

slide67

Recursiveness :

  • Consider a 3-stage Clos network with parameter p0 and q0. Let the rank of a packet from si to di be r0(si)
  • The middle-stage module assigned to the request (si, di) is [r0(si)]q0 which can be obtained by decomposing r0(si) :

r0(si) = α1(q0) + α0

  • Suppose the subnetwork has parameters p1 and q1. The route assignment in the subnetwork is :
slide68

If N = q0q1…qn-1 , number of stages = 2n – 1

The routing tag is : (α0,α1,α2,…,αn-2,βn-1,βn-2,…,β1,β0)

slide69

s

0

1

3

d

1

2

4

r

0

1

2

0000

0001

0010

0001

0010

0100

R=α0α1α2β3β2β1β0

0000001

1000010

0100100

s

4

7

8

10

12

13

d

6

9

10

12

14

15

r

3

4

5

6

7

8

0011

0100

0101

0110

0111

1000

0110

1001

1010

1100

1110

1111

R

1100110

0011001

1011010

0111100

1111110

0001111

Example :

Benes network: qi = 2 for all i

slide70

0

0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

8

8

9

9

10

10

11

11

12

12

13

13

14

14

15

15

fig 3 34 dividing a clos network into two half clos networks

Clos Network

Reverse Omega Network

Omega Network

Fig. 3.34. Dividing a Clos network into two half-Clos networks

General Clos-type Networks :

fig 3 35 an omega network

si

bi ai

ai bi

q= 3

xi

ai

p= 4

xi yi

di

00

00

0

0

0

0

00

0

0

01

01

1

1

01

1

1

02

02

2

2

02

2

2

03

3

10

0

1

10

3

3

11

1

11

4

4

10

1

0

12

2

12

5

5

11

1

12

2

0

2

20

20

13

3

6

6

21

1

21

7

7

22

2

22

8

8

20

2

0

30

0

3

30

21

1

9

9

31

22

2

1

31

10

10

32

23

3

2

32

11

11

Non-blocking if and only if ai = aj → xi ≠ xj

Routing tag for output xi yi : (xi, yi)

Fig. 3.35. An omega network

The Omega Network :

fig 3 36 a reverse omega network

si

aibi

p = 4

xi

ai

q = 3

xi yi

yi xi

di

00

0

0

0

0

00

00

0

0

01

1

1

01

01

1

1

02

2

2

02

02

2

2

3

03

10

1

0

10

3

3

11

1

11

4

4

0

1

10

12

2

12

5

5

1

11

2

12

20

2

0

3

13

20

6

6

21

1

21

7

7

22

2

22

8

8

0

2

20

30

3

0

30

1

21

9

9

31

1

2

22

31

10

10

32

2

3

23

32

11

11

Non-blocking if and only if ai = aj → xi ≠ xj

Routing tag for output yi xi : (xi, yi)

Fig. 3.36. A reverse omega network

The Reverse Omega Network :

fig 3 37 combining a reverse omega network and an omega network

Reverse Omega network

Omega network

stage 1

2

3

4

5

0

0

00

0

0

0

0

00

00

00

00

0

0

0

0

00

1

1

01

1

1

01

01

01

01

1

1

01

2

2

02

2

2

02

02

02

02

2

2

02

3

03

03

3

3

3

10

1

0

10

10

0

1

10

4

4

11

1

11

11

1

11

0

1

10

10

1

0

5

5

12

2

12

12

2

12

1

11

11

1

2

12

12

2

6

6

20

2

0

0

2

20

3

13

20

20

13

3

7

7

21

1

21

21

1

21

8

8

22

2

22

22

2

22

0

2

20

20

2

0

9

9

30

3

0

30

30

0

3

30

1

21

21

1

10

10

31

1

2

22

31

31

22

2

1

31

11

11

32

2

3

23

32

32

23

3

2

32

Fig. 3.37. Combining a reverse omega network and an omega network

Cascade combination :

slide75

p x p

MIN

MIN-1

si

N inputs

N outputs

di

.

.

.

.

.

.

.

middle

stage

(n-1) stages

.

.

.

.

.

(n-1) stages

.

.

.

.

.

.

Cascading a MIN and its reverse network results in a

general Clos-type network :

Unique path for each input-output pair in MIN and

its reverse network

Total N/p alternate paths in Clos-type network

slide76

Concentration required

Contention resolution

by the Three-phase

Algorithm [3]

+

sorting network

omega network

Concentration required

Contention resolution

consists only of two

phases.

Generalization of the

sort-banyan principle

+

sorting network

omega network

Self-Routing Properties of Sort-Clos Network Problems :

[3]J.Y. Hui and E. Arthurs, “A Broadband Switch for Integrated Transport”, IEEE JSAC, Vol. SAC-5, No. 8, Oct. 1987, pp. 1264-1273

slide77

Multicast connections :

  • Extension to broadcast Clos network
  • Let the set of active inputs be (s0,s1,…,sn-1)

Let their corresponding sets of outputs be (D0,D1,…,Dn-1)

The set of connection requests is monotonic if

  • Non-blocking route assignment by the Rank-based Assignment Algorithm
slide78

si

2

3

4

5

8

Di

0,1

2,3,4

5,6

7,8,9

10,11

m + i

0

1

2

3

4

f (si, di) = [m + i]q

0

1

2

0

1

0

00

00

0

1

01

01

1

2

02

02

2

3

10

10

3

4

4

11

11

5

12

12

5

6

20

20

6

7

21

21

7

8

22

22

8

9

9

30

30

10

10

31

31

11

32

32

11

An example :

slide79

Routing and replication :

  • Routing from input to middle-stage modules by decomposing the rank :
  • Routing tag to middle-stage module : (α0,α1,…,αn-2)
  • Replication and routing controlled by the General Interval Splitting Algorithm
slide80

Suppose a node a stage receives a packet with address interval specified by:

  • The bases of mi and Mi are

General Interval Splitting Algorithm :

  • Each packet is assigned an address interval represented by minimum and maximum

min (i-1) = mn-1 … m2n-2

max (i-1) = Mn-1 … M2n-2

  • Replication is controlled by the digits mi and Mi
slide81

General Interval Splitting Algorithm (continued) :

The following procedure is performed :

  • If mi = Mi , then send the packet out on link mi
  • If mi≠ Mi , then (Mi - mi + 1) copies are required Replicate the packet, modify the headers and send the packets out on link mi to Mi
slide82

stage-(i+1)

minimum unchanged

min(i) = min(i-1) = (mn-1 ,…,mi,mi+1 ,…,m2n-2)

max(i) = (mn-1,…, mi, q(2n-2)-(i+1) -1,…, q0-1)

mi

stage-i

j

min(i) = (mn-1 ,…, mi-1, j, 0, …, 0)

max(i) = (mn-1,…, mi-1, j, q(2n-2)-(i+1) -1,…,q0-1)

Mi

.

.

.

.

.

.

.

.

.

.

.

.

.

.

min(i) = (Mn-1 ,…, Mi, 0, …, 0)

max(i) = max(i-1) = (Mn-1,…,Mi,Mi+1,…,M2n-2)

maximum unchanged

.

.

.

.

.

.

.

Header modifications :

slide83

000

000

002

002

001

001

002

002

010

012

010

010

002

101

002

012

011

011

012

012

100

100

101

100

101

101

100

101

102

102

110

110

111

111

112

112

An example :

slide84

Reverse Omega network

Omega network

stage 0

1

2

3

4

00

0

0

0

0

00

00

00

00

0

0

0

0

00

01

1

1

01

01

01

01

1

1

01

02

2

2

02

02

02

02

2

2

02

3

03

03

3

10

1

0

10

10

0

1

10

1

11

11

11

1

11

0

1

10

10

1

0

12

2

12

12

2

12

1

11

11

1

2

12

12

2

20

2

0

0

2

20

3

13

20

20

13

3

21

1

21

21

1

21

22

2

22

22

2

22

0

2

20

20

2

0

30

3

0

30

30

0

3

30

1

21

21

1

31

1

2

22

31

31

22

2

1

31

32

2

3

23

32

32

23

3

2

32

Decomposition and generalization :

slide85

Running Adder

Network (RAN)

and

Dummy Address

Encoders

(DAE’s)

Concentrator

Network

Broadcast

Banyan

Network

(BBN)

Trunk

Number

Translator

(TNT)

Non-blocking copy network based on broadcast banyan network

Running Adder

Network (RAN)

and

Dummy Address

Encoders

(DAE’s)

Broadcast

Clos

Network

Trunk

Number

Translator

(TNT)

Non-blocking copy network based on broadcast Clos network

Generalized copy network architectures :

slide86

Conclusions :

  • The principle governing the non-blocking and self-routing properties of a large class of interconnection networks
  • Non-blocking and self-routing properties of Clos networks
  • Construction of a general Clos-type network by cascade combination of any MIN and its reverse network
  • Extension to multicast network based on broadcast Clos network

~END~