Design Compiler & TetraMAX

Design Compiler & TetraMAX Prepared by Abel Hu

Outline • Design Compiler • overview • setup circuit Environment • setup circuit parameters • Run Compiler • Compile Design • Report Design • TetraMAX- Automatic Test Pattern Generator • Sequential Test Generation • 參考資料

Design Compiler 簡介 • SYNOPSYS公司所發展的軟體Design Compiler, 主要用來做Logic Synthesis。 • 在Cell-Based Flow中扮演著非常重要的角色,透過Design Compiler可以將您所寫好的RTL Verilog或是VHDL Code轉成Gate-Level Netlist。 • 此外還可以搭配現有的Design Wave Library來完成設計, 以及設定Constraint來達成Performance Optimization。

Cell Based Design Flow

Getting Start Synopsys Design Vision • Design Ware datasheet : - http://www.synopsys.com/products/designware/buildingblock.html • Cell Library : .synopsys_dc.setup • HDL File (s) : your_design.v • Command : dv & • Check : File -> setup • Reading Desgin File : (two ways) • File -> Analyze (all file .v) and File -> Elaborate (top .v) • File -> Read (all file .v) • 3. Setting the current design <more> • 4. Setting the Design Environment <more> • Setting the Design Constraints <more> • Setting Design Rule Constraints • Setting Optimization Constraints <more> • 6. Compiling the Design <more> • 7. Saving the Design Database <more> • 8. Reports <more>

.synopsys_dc.setup format company = "CIC"; designer = "Student"; search_path = {. <Your_Full_Path>/CBDK018_UMC_Artisan/CIC/SynopsysDC } + search_path ; link_library = {"fast.db", "slow.db","dw_foundation.sldb"}; target_library = {"fast.db","slow.db"}; symbol_library = {"generic.sdb"} ; synthetic_library = {"dw_foundation.sldb"};

Start using Design Compiler • 我們將以一個ISCAS89 Benchmark circuit 當作執行Design Compiler的範例 • 範例電路名稱: s27.v (netlist) # 4 inputs # 1 outputs

Design Compiler 在console鍵入dv&，即可執行Design Compiler 此軟體介面為GUI圖形，方便使用者操作

Design Compiler - Read File 讀取s27.v 電路 Design Compiler 可以支援不同的formats Verilog: .v VHDL: .vhd System Verilog: .sv EDIF PLA(Berkeley Espresso):.pla

Design Compiler - Read Circuit 這邊可以很清楚看到電路結構的元件將top Module 指向為最上層之電路名稱

Design Compiler - Symbol View 可以顯示電路圖

Design Compiler - Schematic View 可以指定某個元件之顯示圖

Design Compiler - Setting Design Rule Constraints & Optimization Constraints

Design Compiler • Why need to setup circuit Environment? • 1.設定clock可以讓design compiler確定電路是否有 timing violation (Report timing),同時也可確定在電路中可能出現之critical path 之路徑 • 2.盡量符合電路真正實際使用情況 • Operating Environment (工作電壓及環境溫度) • Wire load module (對應至台積電.18製程)

Design Compiler – setup clock 可以指定clock的週期

Design Compiler – Operating Environment “Single” typical – typical for normal design “Min/max case” slow – fast for conservative design 在此可以設定電路一些操作狀況，對應到tsmc18製程

Design Compiler - Select one of the wire load model 可以根據使用者的需要，設定線路的wire load

Design Compiler • Why need to setup circuit parameters • 做最佳化合成過程時,design compiler會將使用者所設定之參數合成至電路中,讓電路有最佳化之表現

Design Compiler - Design Constraints • Max area : 0 • to get the min. area

Design Compiler - Design Constraints • Select the in/out pin which you want to specify 根據使用者的需求,可以設定input timing

Design Compiler - Compile the design(執行最佳化) • Choose Design > Compile Design. • Map effort : medium • Area effort : medium • Click “Ok” to begin compiling.

Design Compiler - Saving the Design Database File -> Save info -> Design Setup ( your_design.dc) save all your design constraints, you may load it : File -> Execute Script ... File -> Save info -> Design Timing (your_design.sdf) Save delay timing information with Standard Delay Format v1.0. It will be referenced during gate level simulation. 可以儲存元件之delay timing,之後將可以在simulation中用到

Design Compiler - Save synthesis result • File - > Save as -> select Format (Verilog) 將合成完成之電路儲存

Design Compiler – saving netlist save as a new gate level code=>gate level code (ex: s27_opt.v)

Design Compiler- Check_test Check_test Design Compile 會確定是否有測試中的violation

Design Compiler – write out *.spf write_test_protocol –format stil –out filename.spf Ex:(s27_opt.spf) 之後將用於TetraMAX

Design Compiler- Report timing Report timing 讓使用者知道是否電路有違反timing violation

Design Compiler- Report wire load Report wire load 提示使用者電路中R(電阻) C(電容)之值

Design Compiler- Report area Report area 提示電路面積

Design Compiler-file format • 以上電路合成最佳化步驟完成之後,各項參數分別可以讓使用者對應至不同level • *.sdf (Standard Delay Format),在執行simulation時,可以讓simulator知道各個元件之delay time(可應用至Verdi) • *.spf ( STIL Protocol File),提供給TetraMAX知道電路在測試過程中的signal , timing, load and unload 等資訊

TetraMAX 簡介 • TetraMAX是一套Test Pattern(測試向量)產生及Fault Simulation(障礙模擬)的軟體，使用者在使用此軟體前，需先準備好電路的HDL code及SPF(STIL Protocol File)檔，輸入後，即可對電路產生Test Pattern。 • 另外亦可輸入已存在的Functional Pattern，以求Pattern的Fault Coverage(障礙涵蓋率)。

TetraMAX - Supported Fault Models • TetraMAX offers three different ATPG modes: • Basic-Scan • Fast-Sequential • Full-Sequential • TetraMAX supports test pattern generation for five types of fault models: • stuckatfaults • IDDQ faults • transition delay faults • path delay faults • and bridgingfaults

Stuck At Faults • The stuck-at fault model is the standard model for test pattern generation. • This model assumes that a circuit defect behaves as a node stuck at 0 or 1. Fig : Stuck-at-0 Fault on Output Pin of 2-input AND Gate

TetraMAX – using TetraMAX • 在使用TetraMAX之前需要準備netlist file及*.spf file 給TetraMAX，可以經由design Compile 產生，順序如下： • 將電路做參數設定，完成之後執行最佳化(run compiler) • Run check_test確定電路是否有violation • Write verilog netlist, 將已經最佳化之電路write out • Write spf file, 此file包含TetraMAX所需要之電路信號設定

TetraMAX – read netlist & lib file Open TetraMAX tool for Sequential Test Pattern Generation

TetraMAX – setup top module 執行build，選擇所需要測試之module =>Build =>選擇 s27 => run

TetraMAX – read *.spf DRC: Design Rule Check主要檢查電路是否有設計上的 violation Run DRC，chose test protocol file(*.spf)

TetraMAX – setup ATPG ATPG: Automatic Test Pattern Generator 自動測試圖樣產生器 Pattern source => 選擇test pattern之來源 Fault source => 選擇要測試之fault Fault model => 選擇要測試之fault類型

TetraMAX – ATPG Report ATPG Report

TetraMAX – write out test pattern file Write test pattern files

TetraMAX – Run fault simulation Run Fault Simulation

TetraMAX – GSV GSV : 提供使用者圖形介面,目的可以讓使用者針對fault做trace的動作

參考資料 - Fault Lists • TetraMAX maintains a list of potential faults for a design, together with the categorization of each fault. • You can read and write fault list files with the read faults and write faults commands. Example: Typical Fault List File Showing Equivalent Faults

參考資料 - equivalent faults • Each entry consists of three items separated by one or more spaces. • The first item indicates the stuck-at value (sa0 or sa1) • the second item is the two-character fault class code • the third item is the pin path name to the fault site • If the fault list contains equivalent faults, then the equivalent faults must immediately follow the primary fault on subsequent lines.

Design Compiler & TetraMAX