Digital integrated circuit design
Download
1 / 41

Digital Integrated Circuit Design - PowerPoint PPT Presentation


  • 233 Views
  • Uploaded on

Digital Integrated Circuit Design. Andrea Bonfanti DEIB Via Golgi 40, Milano. Manufacturing Process. CMOS Process. n-well CMOS Process. Twin-well CMOS Process. Twin-well Trench-Isolated CMOS Process. Triple-well CMOS Process. Circuit Under Design. Its Layout View. nwell. metal1.

loader
I am the owner, or an agent authorized to act on behalf of the owner, of the copyrighted work described.
capcha
Download Presentation

PowerPoint Slideshow about 'Digital Integrated Circuit Design' - nitara


An Image/Link below is provided (as is) to download presentation

Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author.While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server.


- - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript
Digital integrated circuit design

Digital Integrated Circuit Design

Andrea Bonfanti

DEIB

Via Golgi 40, Milano

ManufacturingProcess


Cmos process
CMOS Process

n-well CMOS Process


Twin well cmos process
Twin-well CMOS Process

Twin-well Trench-Isolated CMOS Process




Its layout view
Its Layout View

nwell

metal1

n+ diffusion

poly

p+ diffusion

n+ diffusion

contact

p+ diffusion





Photo lithographic process
Photo-Lithographic Process

optical

mask

oxidation

photoresist

photoresist coating

removal (ashing)

stepper exposure

Typical operations in a single

photolithographic cycle (from [Fullman]).

photoresist

development

acid etch

process

spin, rinse, dry

step


Patterning of sio 2
Patterning of SiO2

Chemical or plasma

etch

Si-substrate

Hardened resist

SiO

2

(a) Silicon base material

Si-substrate

Photoresist

SiO

2

(d) After development and etching of resist,

chemical or plasma etch of SiO

2

Si-substrate

Hardened resist

(b) After oxidation and deposition

SiO

of negative photoresist

2

Si-substrate

UV-light

Patterned

(e) After etching

optical mask

Exposed resist

SiO

2

Si-substrate

Si-substrate

(f) Final result after removal of resist

(c) Stepper exposure


Cmos process at a glance

Define active areas

Etch and fill trenches

Implant well regions

Deposit and pattern

polysilicon layer

Implant source and drain

regions and substrate contacts

Create contact and via windows

Deposit and pattern metal layers

CMOS Process at a Glance


Cmos process walk through

p-epi

(a) Base material: p+ substrate

with p-epi layer

+

p

Si

N

3

4

SiO

(b) After deposition of gate-oxide and

2

p-epi

sacrificial nitride (acts as a

buffer layer)

+

p

(c) After plasma etch of insulating

trenches using the inverse of

the active area mask

p

+

CMOS Process Walk-Through


Cmos process walk through1

SiO

2

(d) After trench filling, CMP

planarization, and removal of

sacrificial nitride

n

(e) After n-well and

V

adjust implants

Tp

p

(f) After p-well and

V

adjust implants

Tn

CMOS Process Walk-Through


Cmos process walk through2

poly(silicon)

(g) After

polysilicon deposition

and etch

n

+

+

p

(h) After

n

+

source/drain and

p

+

source/drain implants. These

steps also dope the polysilicon.

SiO

2

(i) After deposition of SiO

2

insulator and contact hole etch.

CMOS Process Walk-Through


Cmos process walk through3

Al

(j) After deposition and

patterning of first Al layer.

Al

SiO

2

(k) After deposition of SiO

2

insulator, etching of via’s,

deposition and patterning of

second layer of Al.

CMOS Process Walk-Through





3d perspective
3D Perspective

Polysilicon

Aluminum


Design rules1
Design Rules

  • Interface between designer and process engineer

  • Guidelines for constructing process masks

  • Unit dimension: minimum line width

    • scalable design rules: lambda parameter

    • absolute dimensions (micron rules)


Single well cmos process layers

Layer

Color

Representation

Well (n)

Yellow

Active (diffuision n+ or p+)

Green

Select (n+)

Green

Polysilicon

Red

Metal1

Blue

Metal2

Magenta

Contact To Poly

Black

Contact To Diffusion (ntap, ptap)

Black

Via

Black

Single-well CMOS Process Layers


Layers in 0 25 m m cmos process
Layers in 0.25 mm CMOS process












Packaging requirements
Packaging Requirements

  • Electrical: lowparasitics

  • Mechanical: reliable and robust

  • Thermal: efficient heat removal

  • Economical: cheap









ad