Optimal digital circuit design

1. Optimal digital circuit design Mohammad Sharifkhani

2. Outline • Introduction • Optimization for speed • Logical effort • Optimization considering power consumption

3. Optimization for speed • Assume we want to design a multi-stage block that does a special function • What is the best sizes of the transistors to achieve optimal speed?

4. Logical effort • What is the best circuit topology for a function? o How large should the transistors be? o How many stages of logic give least delay? • Logical Effort is a method of answering these questions: o Uses a very simple model of delay o Back of the envelope calculations and tractable optimization o Gives new names to old ideas to emphasize remarkable symmetries • Who cares about logical effort? o Circuit designers waste too much time simulating and tweaking circuits o High speed logic designers need to know where time is going in their logic o CAD engineers need to understand circuits to build better tools

5. Example • Decoder specification: o 16 word register file o Each word is 32 bits wide o Each bit presents a load of 3 unit-sized transistors o True and complementary inputs of address bits a<3:0> are available o Each input may drive 10 unit-sized transistors o How many stages to use? o How large should each gate be? o How fast can the decoder operate?

6. Delay of a gate

7. Normalized delays • Delay is expressed in terms of a basic delay unit, τ = 3RC, the delay of an inverter driving an identical inverter with no parasitic capacitance • In a typical 600-nm process τ is about 50 ps. For a 250-nm process, τ is about 20 ps. In modern 45 nm processes the delay is approximately 4 to 5 ps.

8. Normalized delays • Parasitic delay, p : an intrinsic delay of the gate and can be found by considering the gate driving no load • Stage effort, f = gh: dependent on the load • Logical effort, g: the ratio of the input capacitance of a given gate to that of an inverter capable of delivering the same output current • a constant for a particular class of gate and can be described as capturing the intrinsic properties of the gate • Electrical effort, h: the ratio of the input capacitance of the load to that of the gate • d = f + p

9. Logical effort/Electrical effort

10. Computing logical effort

11. Logical effort and parasitic delay Note: for any inverter size!

12. Example

13. Example

14. Multi-stage paths • It can quickly be extended to circuits composed of multiple stages. • Total normalised path delay D =overall path effort, F, plus path parasitic delayP (which is the sum of the individual parasitic delays): • D = F + P • Path effort , F = G x H • path logical effortG : the product of the individual logical efforts of the gates • path electrical effortH :the ratio of the load of the path to its input capacitance

15. Multi-stage paths

16. Branching effort

17. Branching effort

18. Branching effort • branching effort, b: the ratio of total capacitance being driven by the gate to the capacitance on the path of interest

19. Branching effort

20. Total delay • The total delay of a path is the sum of individual effort delays fi and parasitic delays pi

21. Key point • How to relate individual effort delays to total path effort delay? Lowest possible path delay can be found without even calculating the sizes of each gate in the path. 

22. Gate sizing • Gate sizes can be found by starting at the end of the path and working backward. • Check your work by verifying that the input capacitance specification is satisfied at the beginning of the path.

23. Example 1

24. Example 1

25. Optimal number of stages

26. Optimal number of stages n1 F: Path effort

27. Optimal number of stages For inverter chain:

28. Example • Decoder specification: o 16 word register file o Each word is 32 bits wide o Each bit presents a load of 3 unit-sized transistors o True and complementary inputs of address bits a<3:0> are available o Each input may drive 10 unit-sized transistors o How many stages to use? o How large should each gate be? o How fast can the decoder operate?

29. Example

30. Example Three other inputs create 8 different paths, only one of which is active: Ctotal/Cactive=8

31. Example

32. Example g of 4 input NAND

33. Example

34. Summary

35. Method of Logical Effort

36. Limitation • Logical effort is not a panacea. Some limitations include: o Chicken & egg problem • how to estimate G and best number of stages before the path is designed o Simplistic delay model • neglects effects of input slopes o Interconnect • iteration required in designs with branching and non-negligible wire C or RC • same convergence difficulties as in synthesis / placement problem o Maximum speed only • optimizes circuits for speed, not area or power under a fixed speed constraint

37. Conclusion • Logical effort is a useful concept for thinking about delay in circuits: o Facilitates comparison of different circuit topologies o Easily select gate sizes for minimum delay o Circuits are fastest when effort delays of each stage are equal and about 4 o Path delay is insensitive to modest deviations from optimal sizes • Some further results from logical effort include: o Logical effort can be applied to domino, pass gate, and other logic families o Logic gates can be skewed to favor one input or edge at the cost of another o While the logical effort of a multiplexer is independent of the number of inputs, parasitic delay increases with size, so 4-way multiplexers are best o Circuits that fork should equalize delays between legs of the fork