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Digital Circuit Design on FPGA

Digital Circuit Design on FPGA

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Digital Circuit Design on FPGA

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  1. Digital Circuit Design on FPGA Nattha Jindapetch November 2008

  2. Agenda • Design trends • IC technology revolution • Design styles • System integration • Programmable logic • FPGA design flow & Tools • LABs

  3. IC Technology Revolution

  4. Invention of the Transistor • 1947: first point contact transistor at Bell Labs

  5. The First Integrated Circuit • 1966: ECL 3-Input gate at Motorola

  6. MOS Integrated Circuits • 1970’s processes usually had only nMOS transistors • Inexpensive, but consume power while idle Intel 1101 256-bit SRAM Intel 4004 4-bit Proc 1000 Trs, 1 MHz operation

  7. High Performance Processors • 2001: Intel Pentium Microprocessor • 42 M transistors, • 1.5 GHz operation • CMOS, Low power

  8. Moore’s Law • Transistor counts have doubled every 2 years Integration Levels SSI: 10 gates MSI: 1000 gates LSI: 10,000 gates VLSI: > 10k gates

  9. Corollaries • Many other factors grow exponentially • Ex: clock frequency, processor performance

  10. Evolution of a Revolution • www.intel.com

  11. Design Styles

  12. Design Styles • Full-custom ASIC • Cell-based ASIC • Gate array • Programmable logic • Field programmable gate array (FPGA) • Programmable logic device (PLD) • Complex PLD (CPLD)

  13. Full-Custom ASIC • layout-based • the designer draws each polygon “by hand” • More compact design but longer design time • only for analogue and high(est) volumes

  14. Cell-Based ASIC • used predefined building blocks (“cells”) • designer creates a schematic that interconnects these cells • layout = placement & interconnection of cells • for “functionality” or “time-to market” driven design

  15. Gate Array • Each chip is prefabricated with an array of identical gates or cells. • The chip is “customized” by fabricating routing layers on top. • Time to market, cost

  16. Field programmable gate array • Chips are prefabricated with logic blocks and interconnects. • Logic and interconnects can be programmed (erased and reprogrammed) by users. • No fabrication is needed. • Cost efficient for medium complexity (< 1M gates) designs

  17. PLD and CPLD • Programmable Logic Device (PLD, PLA, PAL, ...) • AND-OR combinatorial logic, plus FF • designer writes Boolean equations • Small complexity only • Complex PLD (CPLD) • several PLD blocks • programmable interconnection matrix

  18. Trends in Design styles • More complex system • Digital and Analog IC (Mixed Signal) • Hardware and Software Co-design • SoC, SoPC Resulting in … • Higher abstract design level • Advanced design tools to automate complex designs • Short design time to compete market share

  19. Why HW/SW Co-design? • Hardware (ASIC, FPGA) • Fast • But very expensive • Software (Processor) • Flexible • But slow • Hardware + Software = Good solution? • Requirements?

  20. Example of Digital Camera

  21. System Integration

  22. System Integration

  23. Benefits • Less components • Component costs • Board size and cost • Assembly and testing costs • Less inter-chip interconnects • Reliability • Power consumption • Board design, fabrication and assembly costs • Smaller system volume (in cm2) and weight • Higher integration rate • Smaller case costs • Smaller transport costs • In high volumes (in pcs), also lower circuit costs

  24. SoP • System-on-Package (SoP) or System-in-Package (SiP) are advanced multi-chip packaging technology complementing SoC.

  25. SoC • System-on-Chip –one term, many definitions • “IBM definition”: a single-chip system containing analog, digital and MEMS (micro-electro-mechanical system) parts • “Lucent definition”: a single-chip system containing analog and digital parts • “Synopsys definition”: a single-chip digital system • SoC, System-on-Chip is a relatively complex standalone system on a single semiconductor chip containing at least one processor, maybe some analog or even electro-mechanical parts, where the design needs to address on-chip communication

  26. SoPC • System-on-a-Programmable Chip (SOPC) term coined by Synopsys • SoPC is a FPGA technology based user programmable solution • P&R and programming done by the user • No delay on prototype production • No delay on mass production start • No NRE (production start) costs • Production tests done by the IC vendor • Design resource and time savings in the design flow • Quick and cheap modifications

  27. SoC vs SoPC • SoC manufacturing is costly • Foundries more and more expensive • Mask costs for fine-grain lithography are increasing • Silicon vendors concentrate on big customers with big quantities • Very few multi-project prototype services available • Malfunction will cost a lot of money and time • Full-wafer prototype round may cost even 500,000 ... 1M € • FPGA-type solutions are also evolving • On-chip processor cores • Multi-million gate capacity • Some vendors also provide coarse-grain reconfigurability • FPGA-based SoC-type platforms thus have a growing niche

  28. Programmable Logic

  29. Programmable Logic • Programmable digital integrated circuit • Standard off-the-shelf parts • Desired functionality is implemented by configuring on-chip logic blocks and interconnections • Advantages (compared to an ASIC): • Low development costs • Short development cycle • Device can (usually) be reprogrammed • Types of programmable logic: • Complex PLDs (CPLD) • Field programmable Gate Arrays (FPGA)

  30. CPLDArchitecture and Examples

  31. A B C AND plane PLD - Sum of Products Programmable AND array followed by fixed fan-in OR gates Programmable switch or fuse

  32. Select B A C Enable Flip-flop MUX D Q Clock AND plane PLD - Macrocell Can implement combinational or sequential logic

  33. I/O Block PLD Block PLD Block I/O Block Interconnection Matrix Interconnection Matrix I/O Block PLD Block PLD Block I/O Block CPLD Structure Integration of several PLD blocks with a programmable interconnect on a single chip

  34. CPLD Example – Altera MAX7000 EPM7000 Series Block Diagram

  35. CPLD Example –Altera MAX7000 EPM7000 Series Device Macrocell

  36. FPGA Architecture

  37. FPGA building blocks: Programmable logic blocksImplement combinatorial and sequential logic Programmable interconnectWires to connect inputs and outputs to logic blocks Programmable I/O blocksSpecial logic blocks at the periphery of device for external connections Logic block Interconnection switches I/O I/O I/O I/O FPGA - Generic Structure

  38. Other FPGA Building Blocks • Clock distribution • Embedded memory blocks • Special purpose blocks: • DSP blocks: • Hardware multipliers, adders and registers • Embedded microprocessors/microcontrollers • High-speed serial transceivers

  39. Select Out LUT A B C D D Q Clock FPGA – Basic Logic Element • LUT to implement combinatorial logic • Register for sequential circuits • Additional logic (not shown): • Carry logic for arithmetic functions • Expansion logic for functions requiring more than 4 inputs

  40. LUT implementation LUT A B Z A C D B Z C D Truth-table Gate implementation Look-Up Tables (LUT) • Look-up table with N-inputs can be used to implement any combinatorial function of N inputs • LUT is programmed with the truth-table

  41. X1 X2 0/1 0/1 0/1 0/1 F 0/1 0/1 0/1 0/1 X3 LUT Implementation • Example: 3-input LUT • Based on multiplexers (pass transistors) • LUT entries stored in configuration memory cells Configuration memory cells

  42. LE LE LE Switch Matrix Switch Matrix LE LE LE Programmable Interconnect • Interconnect hierarchy (not shown) • Fast local interconnect • Horizontal and vertical lines of various lengths

  43. 6 pass transistors per switch matrix interconnect point Pass transistors act as programmable switches Pass transistor gates are driven by configuration memory cells Switch Matrix Operation After Programming Before Programming

  44. Special Features • Clock management • PLL,DLL • Eliminate clock skew between external clock input and on-chip clock • Low-skew global clock distribution network • Support for various interface standards • High-speed serial I/Os • Embedded processor cores • DSP blocks

  45. Configuration Storage Elements • Static Random Access Memory (SRAM) • each switch is a pass transistor controlled by the state of an SRAM bit • FPGA needs to be configured at power-on • Flash Erasable Programmable ROM (Flash) • each switch is a floating-gate transistor that can be turned off by injecting charge onto its gate. FPGA itself holds the program • reprogrammable, even in-circuit • Fusible Links (“Antifuse”) • Forms a forms a low resistance path when electrically programmed • one-time programmable in special programming machine • radiation tolerant

  46. Xilinx Virtex-II/Virtex-4: Feature-packed high-performance SRAM-based FPGA Spartan 3: low-cost feature reduced version CoolRunner: CPLDs Altera Stratix/Stratix-II High-performance SRAM-based FPGAs Cyclone/Cyclone-II Low-cost feature reduced version for cost-critical applications MAX3000/7000 CPLDs MAX-II: Flash-based FPGA Actel Anti-fuse based FPGAs Radiation tolerant Flash-based FPGAs Lattice Flash-based FPGAs CPLDs (EEPROM) QuickLogic ViaLink-based FPGAs FPGA Vendors & Device Families

  47. State of the Art in FPGAs • Xilinx’s top of the line FPGA • 65nm process technology • 550MHz RAM blocks • 6-input LUTs • Serial connectivity • Ethernet MACs • Rocket I/O serial 6.5 GBps • PCI Express endpoint • Enhanced DSP blocks (25x18-bit MAC) • 1760 pin BGA with 1200 I/O • EasyPath

  48. FPGA Design Flow Xilinx Design Flow

  49. LABs • Lab1: Introduction • Quick start • Synthesis results • RTL schematic • Technology schematic • Device utilization summary • Timing summary • Simulation • Behavioral • Post-Place and Route (PAR) Simulation

  50. References • Theerayod Wiangtong, “Design Trends on Digital System Design”, Lecture note, Electronic Department, Mahanakorn University of Technology, 2004 • Fank Mayer, “High-Level IC Design”, Fraunhofer IIS, Erlangen, Germany, 2004 • Stefan Haas, “FPGAs”, CERN Technical Training 2005 • Xilinx University Program, http://www.xilinx.com/support/education-home.htm