Commissioning the ATLAS Silicon Microstrip Tracker

1. ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Commissioning the ATLAS Silicon Microstrip Tracker Jose E. Garcia Université deGenève fortheAtlasSCTcollaboration IPRD08 - Siena

2. 2 ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions ATLAS is being assembled toexploit the 14TeV pp collisions at the LHC ATLAS Detector • The Inner Detector forms the heart of the ATLAS experiment. The closest to the interaction point. • Pixel Detector • Semiconductor Tracker (SCT) • Transition Radiation Detector (TRT) Jose E. Garcia IPRD08 - Siena

3. 3 ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions • 61 m2 of silicon with 6.2 million readout channels • 4088 silicon modules arranged to form 4 Barrels and 9+9 Disks • Barrels : 2112 modules with acceptance || < 1.1 to 1.4 • Endcaps : 1976 modules with acceptance 1.1 to 1.4 <|| < 2.5 • Space point resolution r ~17m / Z ~ 580 m (23 m strip resolution) Semi-Conductor Tracker • Radiation hard: tested to 2x1014 1-MeV neutron equivalent /cm2 • Material: 3% X0 per layer ( = 0) Jose E. Garcia IPRD08 - Siena

4. 4 • Back-to-back sensors, glued to highly thermallyconductive substrates for mechanical stability and sensor cooling • 40mrad stereo angle between sensors • 1536 channels (768 on each side) • Optical communication • 5.6W/module (adding ~1W per sensor after 10 years LHC) • Cooled to -25oC to limit sensor radiation damage and -8oC ambient temperature. • up to 500V sensor bias ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Silicon Modules • 2112 Barrel modules • one module type • 1976 EndCap modules • 4 module types Jose E. Garcia IPRD08 - Siena

5. Data Compression Circuit PreAmp+Shaper Readout Buffer Comparator Edge-Detect circuit Binary Pipeline (132 deep) Test-Input DAC • 3 pipeline bins read out, centered • on L1A trigger Threshold Voltage v “Shaped” input pulse to Comparator t “Logic” output of comparator t 5 • 128 channel ASIC with binary architecture • Radiation-hard DMILL technology • 12 chips per module (6 each side) • glued to hybrid (Cu/polyimide flex circuit) • 40MHz (25ns) clock • 20ns front end shaping time • Redundancy scheme (chips, link, TTC) ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Front End Electronics Jose E. Garcia IPRD08 - Siena

6. 6 ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions • 4 Assembly Sites • Oxford - Barrel • Nikhef - EndCap A • Liverpool - EndCap C • SR1 at CERN Assembly Sites Jose E. Garcia IPRD08 - Siena

7. 7 ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Installation Timeline Barrel in Pit EndCaps in Pit Pixels in Pit • TestModuleconnectivity and performance comparing withsurfacedata ID sealed • Cooling Issues • 3 ID compressors failed • 100 kg of C3F8 lost and 900 contaminated • Cooling plant cleaned up and broken parts replaced • Fortunately detector not affected • Measures have been taken to prevent this to happen again ID operational in Atlas Jose E. Garcia IPRD08 - Siena

8. 8 • Electrical Connections • Check LV arrives at modules: VDD, VCC, IPIN, IVCSEL • HV current voltage scan • Check temperature readings • Optical Connections • P-i-n current checks • Light from fiber data measured at Redaout Driver (ROD) • Check fiber connection and correct module mapping • Calibration Tests • Digital and Analogue functionality tested • Gain curve, Noisy/Dead channel map • Noise occupancy Tests • Cosmic Tests • Milestone 6 (M6) : • Global commissioning run with ATLAS ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Commissioning Tests Combined SCT and TRT track. Jose E. Garcia IPRD08 - Siena

9. 9 • Since middle of August cooling is back and running stably for the detectors. • SCT running fully powered since end August ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions • Calibration and configuration changes are being made to improve performance. Some modules were removed from due to readout issues. They will be back in once they are properly adjusted. Approximate numbers: • Barrel: 99.6% modules • EndCaps (*): 97.8% modules • (*2 out of 72 cooling loops off, partially recoverable during shutdown) • Around 97% configuration for stable readout in ATLAS Atlas Integration • Standalone calibration was performed up to the first week of September. From then SCT has been included in the Atlas data taking • Full Barrel and Endcap ROD readout • Athena and ROS Level Monitoring • Data Quality Monitoring Jose E. Garcia IPRD08 - Siena

10. 10 ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Noise Occupancy • Barrel Noise Occupancy at 150 V • measured ~4.4 x 10-5 • Outer/middle NO of ~ 5 x10-5 • Inner type modules much lower due to short strip length • Values in agreement to measurements from production, integration and installation. Jose E. Garcia IPRD08 - Siena

11. Broken TX fibre or dead PIN Clock and control from neighbouring module Broken TX fibre or dead PIN Clock and control from neighbouring module BOC ROD DATA RX Ch TX Ch TTC 11 Some SCT channels generate no pin current (TX). Suspect ESD damage. ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Current issue: TTC link Currently affected around 2.5 % of the modules • Currently we are using redundancy whenever possible (this is not possible where two adjacent modules have zero pin current). • If a few channels in a specific TX plugin are lost, it will be needed to change them. • Plugins can be replaced at the USA15. Newly manufactured plugins are being tested. Broken TX fibre or dead PIN Clock and control from neighboring module Jose E. Garcia IPRD08 - Siena

12. 12 • Apply global trigger delay offset on top of the 4088 individual delays, • and scan offset to look for increase in number of coincidental hits, increasing the number of space-points and tracks. • Reading 3 bunch crossings (3 x 25 ns clock cycles). • Scans were done and SCT was timed in using cosmics before first beam and continued after • LATER (with beam!): When roughly timed in, start fine delay (steps of 280ps) to tune relative bin occupancies and optimise hit efficiency. Fine scan delay scan with different offsets for each module ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Timing In with ATLAS Jose E. Garcia IPRD08 - Siena

13. 13 SCT EndCaps at 20 V during the first beam ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions First Beam (10th Sept) Many tracks and space-points seen during the circulating beam Jose E. Garcia IPRD08 - Siena

14. 14 Data taking is ongoing 24/7 with the rest of the sub-systems. ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Combined Tracks: SCT + Pixels First tracks seen with hits in pixels and SCT combined Jose E. Garcia IPRD08 - Siena

15. The residuals for the SCT barrel show a behaviour similar to the M6 results. 15 The residuals for the SCT barrel show a behavior similar to the M6 results. ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Alignment with Last Cosmics Data Hits on tracks for barrel layers Jose E. Garcia IPRD08 - Siena

16. 16 ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions • SCT running fully powered since beginning of September with 97% configuration for stable readout in ATLAS after the first round of readout adjustments. • Integrated the full SCT into ATLAS combined partition • Observed first beam and used beam splashes to get first timing (on endcaps) • Currently ongoing cosmics runs for: • Timing studies • Alignment • DAQ,DCSandMonitoringtuningup • Improvement on module calibration Conclusions Jose E. Garcia IPRD08 - Siena

17. 17 ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Backup Backup Slides Jose E. Garcia IPRD08 - Siena

18. 18 ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Backup Timing In FINE Trig FINE … x48 Fibres to modules ROD FINE • Compensate for differentpropagation delays ofC&C from BOC to module(which varies from 380nsto 446ns) • 4088 individual delaysfrom 0 to 66ns FINE ROD Crate BOC fine delay up to 35ns in 280ps steps BOC coarse delay Up to 32 clock cycles Jose E. Garcia IPRD08 - Siena

19. 19 ATLAS and ID SCT Commissioning Integration Latest Runs Conclusions Backup Optical Communication Jose E. Garcia IPRD08 - Siena