1 / 14

Csci 136 Computer Architecture II – Summary of MIPS ISA

Csci 136 Computer Architecture II – Summary of MIPS ISA. Xiuzhen Cheng cheng@gwu.edu. Announcement. Homework assignments #2: Readings: Sections 3.6, 3.7, 3.10, 3.11, 3.13, 3.14 Problems 3.5, 3.10, 3.12, 3.22, 3.23, 3.24, 3.25 Project #1 is due on 11:59PM, Feb 13, 2003. What is an ISA?.

martena-clayton
Download Presentation

Csci 136 Computer Architecture II – Summary of MIPS ISA

An Image/Link below is provided (as is) to download presentation Download Policy: Content on the Website is provided to you AS IS for your information and personal use and may not be sold / licensed / shared on other websites without getting consent from its author. Content is provided to you AS IS for your information and personal use only. Download presentation by click this link. While downloading, if for some reason you are not able to download a presentation, the publisher may have deleted the file from their server. During download, if you can't get a presentation, the file might be deleted by the publisher.

E N D

Presentation Transcript

  1. Csci 136 Computer Architecture II– Summary of MIPS ISA Xiuzhen Cheng cheng@gwu.edu

  2. Announcement • Homework assignments #2: • Readings: Sections 3.6, 3.7, 3.10, 3.11, 3.13, 3.14 • Problems 3.5, 3.10, 3.12, 3.22, 3.23, 3.24, 3.25 • Project #1 is due on 11:59PM, Feb 13, 2003.

  3. What is an ISA? • A very important abstraction • Provide the interface between the low-level software and hardware • May have multiple hardware implementations • Needs to answer the following questions • What is the minimum instruction set to be supported? • Use general purpose register or not? • CIRS or RISC design? • Instruction format? • Addressing mode? • … …

  4. Register Register (register-memory) (load-store) Load R1,A Add R1,B Store C, R1 Basic ISA Classes • Accumulator Architecture • Stack Architecture • Load-Store (General Purpose Register) Architecture • Register – Register • Register – Memory • Memory – Memory • Code sequences for (C=A+B) for 4 classes of instruction set Stack Accumulator Push A Load A Load R1,A Push B Add B Load R2,B Add Store C Add R3,R1,R2 Pop C Store C,R3

  5. ° Since 1975, all machines use general purpose registers ° Advantages of registers • registers are faster than memory • registers are easier for a compiler to use e.g., (A*B) – (C*D) – (E*F) can do multiplies in any order - vs. stack • registers can hold variables - memory traffic is reduced, so program is sped up (since registers are faster than memory) code density improves (since register named with fewer bits - than memory location) General Purpose Register Dominates

  6. Memory Addressing ° Since 1980 almost every machine uses addresses to level of 8-bits (byte) ° 2 questions for design of ISA: • Since one could read a 32-bit word as four loads of bytes from sequential byte addresses or as one load word from a single byte address, How do byte addresses map onto words? Can a word be placed on any byte boundary? • What about MIPS?

  7. ISA Operation Summary • Support these simple instructions, since they will dominate the number of instructions executed: • load, • store, • add, • subtract, • move register-register, • and, • shift, • compare equal, compare not equal, • branch, jump, • call, • return;

  8. Summary: Salient features of MIPS • 32-bit fixed format inst (3 formats) • 32 32-bit GPR (R0 contains zero) and 32 FP registers (and HI LO) • partitioned by software convention • 3-address, reg-reg arithmetic instr. • Single addressing mode for load/store: base+displacement • no indirection, scaled • 16-bit immediate plus LUI • Simple branch conditions • compare against zero or two registers for =, • no integer condition codes

  9. Summary: MIPS Instruction set design • Use general purpose registers with a load-store architecture: yes or no? • Provide 32 general purpose registers plus separate floating-point registers: • What’s the addressing mode supported by MIPS? • Use fixed instruction encoding if interested in performance and use variable instruction encoding if interested in code size :

  10. Summary: MIPS Instruction set design • Support these data sizes and types: 8-bit, 16-bit, 32-bit integers and 32-bit and 64-bit IEEE 754 floating point numbers: • Support these simple instructions, since they will dominate the number of instructions executed: load, store, add, subtract, move register-register, and, shift, compare equal, compare not equal, branch, jump, call, and return: • Aim for a minimalist instruction set:

  11. MIPS Hardware Design Principles • Simplicity favors regularity • Keeping the hardware simple! • R-Type instruction format • Smaller is faster • 32 general purpose registers, no more, no less. • Good design demands good compromises • R, I, J, 3 types of instruction formats • Make the common case fast! • I-type instructions for constant numbers

  12. In-Class Exercise: Reverse a String • Write a MIPS procedure to reverse a null-terminated character string. Assume the address of the string is in $a0 and the address of the reversed string is in $a1. Also assume the spaces needed by the reversed string have been pre-allocated.

  13. In-Class Exercise: Reverse a String • Write a MIPS procedure to reverse a null-terminated character string. Assume the address of the string is in $a0 and the address of the reversed string is in $a1. Also assume the spaces needed by the reversed string have been pre-allocated. reverseStr: addiu $sp, $sp, -32 sw $s0, 16($sp) sw $s1, 20($sp) move $s0, $a0 move $s1, $a1 addi $sp, $sp, -1 sb $zero, 0($sp) push: lbu $t0, 0($s0) beq $t0, $zero, pop addi $s0, $s0, 1 addi $sp, $sp, -1 sb $t0, 0($sp) j push pop: lbu $t0, 0($sp) addi $sp, $sp, 1 sb $t0, 0($s1) beq $t0, $zero, done addi $s1, $s1, 1 j pop done: lw $s0, 16($sp) lw $s1, 20($sp) addi $sp, $sp, 32 jr $ra

  14. Questions?

More Related