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CSE313 Computer Architecture. Arithmetic for Computers. Outline for the lectures. Some arithmetic fundamentals Division of hardware into integer and floating point computation Designing an integer Arithmetic Logic Unit (ALU) for MIPS Integer addition Integer multiplication

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## CSE313 Computer Architecture

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**CSE313 Computer Architecture**Arithmetic for Computers**Outline for the lectures**• Some arithmetic fundamentals • Division of hardware into integer and floating point computation • Designing an integer Arithmetic Logic Unit (ALU) for MIPS • Integer addition • Integer multiplication • Integer division • Floating point representation • Floating point computation • MIPS floating point registers • MIPS floating point instructions**Some arithmetic fundamentals**• Unsigned numbers: values are always positive • Example: 1000 10102 = 27+23+21=14610 • Signed numbers: two’s complement notation • Example: 1000 10102 = -27+23+21=-11810 • Leftmost bit called the sign bit • Positive numbers have a sign bit of 0, negative numbers a sign bit of 1 • Sign extending a number: replicate the most significant bit the number of times needed • Example: 1000 10102 is the same as 1111 1111 1000 10102**Some arithmetic fundamentals**• Negating a two’s complement number: invert (NOT) all bits and add 1 • Example: negative of 1000 1010 = 0111 0101 + 1 = 0111 0110 = 118 • Logical operations • AND, OR, NOR, XOR perform logic function on a bit-by-bit basis • Example: 1000 1010 AND 1101 0110 = 1000 0010 • Also arithmetic/logical shift left/right**Integer and floating point computation**• Most general-purpose ISAs specify separate integer and floating point register files • Operand representation formats differ • Computation hardware differs • Result is a split of the execution core into integer and floating point sections integer ALU data memory integer register file instruction memory P C integer multiplier flt pt adder flt pt register file flt pt multiplier**604e microprocessor**integer register file and execution units flt pt register file and execution units**Designing an integer ALU for MIPS**• ALU = Arithmetic Logic Unit • Performs single cycle execution of simple integer instructions • Supports add, subtract, logical, set less than, and equality test for beq and bne • Both signed and unsigned versions of add, sub, and slt**ALU block diagram**• Inputs • a,b: the data (operands) to be operated on • ALU operation: the operation to be performed • Outputs • Result: the result of the operation • Zero: indicates if the Result = 0 (for beq, bne) • CarryOut: the carry out of an addition operation • Overflow: indicates if an add or sub had an overflow (later)**Basic integer addition**• Pencil-and-paper binary addition • Full adder sum and carry equations for each bit (CarryIn) a b (CarryOut) Sum**1-bit ALU bit-slice**• Bit-slice design: create a building block of part of the datapath (1 bit in our example) and replicate it to form the entire datapath • ALU bit-slice supporting addition, AND, OR • 1-bit AND, 1-bit OR, 1-bit full add of a and b always calculated • Operation input (2 bits) determines which of these passes through the MUX and appears at Result • CarryIn is from previous bit-slice • CarryOut goes to next bit-slice**Creating a 32-bit ALU from 1-bit bit-slices**What should we set this to when Operation=10 (add)? • Performs ripple carry addition • Carry follows serial path from bit 0 to bit 31 (slow) (LSB) (MSB)**Handling subtraction**• Perform a+(-b) • Recall that to negate b we • Invert (NOT) all bits • Add a 1 • Set CarryIn input of LSB bitslice to 1 • New bit-slice design**Implementing bne, beq**• Need to detect if a=b • Detected by determining if a-b=0 • Perform a+(-b) • NOR all Result bits to detect Result=0**Implementing Set Less Than (slt)**• Result=1 if a<b, otherwise Result=0 • All bits except bit 0 are set to zero through a new bit-slice input called Less that goes to a 4th input on the bit-slice MUX What do we input here? 3 Less Set to zero for all but LSB**Implementing Set Less Than (slt)**• Set bit 0 to one if the result of a-b is negative and to zero otherwise • a-b=negative number implies that a<b • Feed the adder output of bit 31 to the Less input of bit 0 3 Less Set Only used for MSB**Full 32-bit ALU design**• Bnegate controls CarryIn input to bit 0 and Binvert input to all bit-slices • Both are 1 for subtract and 0 otherwise, so a single signal can be used • NOR, XOR, shift operations would also be included in a MIPS implementation**Overflow**• Overflow occurs when the result from an operation cannot be represented with the number of available bits (32 in our ALU) • For signed addition, overflow occurs when • Adding two positive numbers gives a negative result • Example: 01110000…+00010000…=1000000… • Adding two negative numbers gives a positive result • Example: 10000000…+10000000…=0000000… • For signed subtraction, overflow occurs when • Subtracting a negative from a positive number gives a negative result • Subtracting a positive from a negative number gives a positive result**Overflow**• Overflow on unsigned arithmetic, which is primarily used for manipulating addresses, is ignored in many ISAs (including MIPS) • Overflow on signed arithmetic causes an interrupt to deal with the problem (Chapter 5) • Overflow detection: XOR CarryIn of MSB with CarryOut of MSB**Integer multiplication**• Pencil and paper binary multiplication 1000 (multiplicand) x 1001 (multiplier)**Integer multiplication**• Pencil and paper binary multiplication 1000 (multiplicand) x 1001 (multiplier) 1000**Integer multiplication**• Pencil and paper binary multiplication 1000 (multiplicand) x 1001 (multiplier) 1000 00000**Integer multiplication**• Pencil and paper binary multiplication 1000 (multiplicand) x 1001 (multiplier) 1000 00000 000000**Integer multiplication**• Pencil and paper binary multiplication 1000 (multiplicand) x 1001 (multiplier) 1000 00000 000000 1000000**Integer multiplication**• Pencil and paper binary multiplication 1000 (multiplicand) x 1001 (multiplier) 1000 00000 (partial products) 000000 +1000000 1001000 (product)**Integer multiplication**• Pencil and paper binary multiplication • Key elements • Examine multiplier bits from right to left • Shift multiplicand left one position each step • Simplification: each step, add multiplicand to running product total, but only if multiplier bit = 1 1000 (multiplicand) x 1001 (multiplier) 1000 00000 (partial products) 000000 +1000000 1001000 (product)**Integer multiplication**• 32-bit hardware implementation • Multiplicand loaded into right half of multiplicand register • Product register initialized to all 0’s • Repeat the following 32 times • If multiplier register LSB=1, add multiplicand to product • Shift multiplicand one bit left • Shift multiplier one bit right LSB**Integer multiplication**• Algorithm**Integer multiplication**• Initialize product register to 0 1000 (multiplicand) 1001 (multiplier) 00000000 (running product)**Integer multiplication**• Multiplier bit = 1: add multiplicand to product 1000 (multiplicand) 1001 (multiplier) 00000000 +1000 00001000 (new running product)**Integer multiplication**• Shift multiplicand left 10000 (multiplicand) 1001 (multiplier) 00000000 +1000 00001000**Integer multiplication**• Multiplier bit = 0: do nothing 10000 (multiplicand) 1001 (multiplier) 00000000 +1000 00001000**Integer multiplication**• Shift multiplicand left 100000 (multiplicand) 1001 (multiplier) 00000000 +1000 00001000**Integer multiplication**• Multiplier bit = 0: do nothing 100000 (multiplicand) 1001 (multiplier) 00000000 +1000 00001000**Integer multiplication**• Shift multiplicand left 1000000 (multiplicand) 1001 (multiplier) 00000000 +1000 00001000**Integer multiplication**• Multiplier bit = 1: add multiplicand to product 1000000 (multiplicand) 1001 (multiplier) 00000000 +1000 00001000 +1000000 01001000 (product)**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand 1000 (multiplicand) 1001 (multiplier) 00000000 (running product)**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand 1000 (multiplicand) 1001 (multiplier) 00000000 +1000 10000000 (new running product)**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand 1000 (multiplicand) 1001 (multiplier) 00000000 +1000 01000000 (new running product)**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand 1000 (multiplicand) 1001 (multiplier) 00000000 +1000 01000000 (new running product)**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand 1000 (multiplicand) 1001 (multiplier) 00000000 +1000 00100000 (new running product)**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand 1000 (multiplicand) 1001 (multiplier) 00000000 +1000 00100000 (new running product)**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand 1000 (multiplicand) 1001 (multiplier) 00000000 +1000 00010000 (new running product)**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand 1000 (multiplicand) 1001 (multiplier) 00000000 +1000 00010000 +1000 10010000 (new running product)**Integer multiplication**• Drawback: half of 64-bit multiplicand register are zeros • Half of 64 bit adder is adding zeros • Solution: shift product right instead of multiplicand left • Only left half of product register added to multiplicand 1000 (multiplicand) 1001 (multiplier) 00000000 +1000 00010000 +1000 01001000 (product)**Integer multiplication**• Hardware implementation**Integer multiplication**• Final improvement: use right half of product register for the multiplier**Integer multiplication**• Final algorithm

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