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CS4100: 計算機結構 Computer Arithmetic. 國立清華大學資訊工程學系 一零零 學年度第二學期. Outline. Addition and subtraction (Sec. 3.2) Constructing an arithmetic logic unit (Appendix C) Multiplication (Sec. 3.3, Appendix C) Division (Sec. 3.4) Floating point (Sec. 3.5). Problem: Designing MIPS ALU.

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## CS4100: 計算機結構 Computer Arithmetic

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**CS4100: 計算機結構Computer Arithmetic**國立清華大學資訊工程學系 一零零學年度第二學期**Outline**• Addition and subtraction (Sec. 3.2) • Constructing an arithmetic logic unit (Appendix C) • Multiplication (Sec. 3.3, Appendix C) • Division (Sec. 3.4) • Floating point (Sec. 3.5) Arithmetic-1**Problem: Designing MIPS ALU**• Requirements: must support the following arithmetic and logic operations • add, sub: two’s complement adder/subtractor with overflow detection • and, or, nor : logical AND, logical OR, logical NOR • slt (set on less than): two’s complement adder with inverter, check sign bit of result Arithmetic-2**Functional Specification**ALU Control (ALUop)Function 0000 and 0001 or 0010 add 0110 subtract 0111 set-on-less-than 1100 nor ALUop 4 A 32 Zero ALU Result 32 Overflow B 32 CarryOut Arithmetic-3**A Bit-slice ALU**• Design trick 1: divide and conquer • Break the problem into simpler problems, solve them and glue together the solution • Design trick 2: solve part of the problem and extend 32 A B 32 a0 b0 4 a31 b31 m m ALU0 ALU31 ALUop co cin c31 cin s0 s31 Overflow Zero 32 Result Arithmetic-4**1-bit**Full Adder A 1-bit ALU • Design trick 3: take pieces you know (or can imagine) and try to put them together CarryIn Operation and A 0 or Result 1 Mux add 2 B CarryOut Arithmetic-5**CarryIn**A Result Mux 1-bit Full Adder B CarryOut A 4-bit ALU 1-bit ALU 4-bit ALU Operation CarryIn0 Operation A0 1-bit ALU Result0 B0 CarryOut0 CarryIn1 A1 1-bit ALU Result1 B1 CarryOut1 CarryIn2 A2 1-bit ALU Result2 B2 CarryOut2 CarryIn3 A3 1-bit ALU Result3 B3 CarryOut3 Arithmetic-6**How about Subtraction?**• 2’s complement: take inverse of every bit and add 1 (at cin of first stage) • A + B’ + 1 = A + (B’ + 1) = A + (-B) = A - B • Bit-wise inverse of B is B’ Subtract (Bnegate) CarryIn Operation A ALU Result Sel B 0 Mux 1 B’ CarryOut Arithmetic-7**Supply a 1 on subtraction**Revised Diagram • LSB and MSB need to do a little extra 32 A B 32 a0 b0 4 a31 b31 ALU0 ALU31 ALUop co cin ? c31 cin s0 s31 32 Combining the CarryIn and Bnegate Overflow Zero Result Arithmetic-8**Functional Specification**ALU Control (ALUop)Function 0000 and 0001 or 0010 add 0110 subtract 0111 set-on-less-than 1100 nor ALUop 4 A 32 Zero ALU Result 32 Overflow B 32 CarryOut Arithmetic-9**6**5 5 5 5 6 opcode rs rt rd shamt funct R-Format Instructions (1/2) • Define the following “fields”: • opcode: partially specifies what instruction it is (Note: 0 for all R-Format instructions) • funct: combined with opcode to specify the instruction Question: Why aren’t opcode and funct a single 12-bit field? • rs (Source Register): generally used to specify register containing first operand • rt (Target Register): generally used to specify register containing second operand • rd (Destination Register): generally used to specify register which will receive result of computation Arithmetic-10**a**b 0 0 1 1 Nor Operation • A nor B = (not A) and (not B) ALUop 2 Ainvert Operation CarryIn 0 1 Bnegate Result 2 CarryOut Arithmetic-11**Functional Specification**ALU Control (ALUop)Function 0000 and 0001 or 0010 add 0110 subtract 0111 set-on-less-than 1100nor ALUop 4 A 32 Zero ALU Result 32 Overflow B 32 CarryOut Arithmetic-12**Functional Specification**ALU Control (ALUop)Function 0000 and 0001 or 0010 add 0110 subtract 0111 set-on-less-than 1100 nor ALUop 4 A 32 Zero ALU Result 32 Overflow B 32 CarryOut Arithmetic-13**b**a 0 0 1 1 Set on Less Than (I) • 1-bit in ALU (for bits 1-30) ALUop Ainvert Operation CarryIn 0 1 Bnegate Result 2 3 Less (0:bits 1-30) CarryOut Arithmetic-14**0**0 1 1 Set on Less Than (II) • Sign bit in ALU Operation Ainvert CarryIn a 0 Bnegate 1 Result b 2 3 Less Set Overflow detection Overflow Arithmetic-15**b**a 0 0 1 1 Set on Less Than (III) • Bit 0 in ALU ALUop Ainvert Operation CarryIn 0 1 Bnegate Result 2 3 Set CarryOut Arithmetic-16**A Ripple Carry Adder and Set on Less Than**ALUop Function 0000 and 0001 or 0010 add 0110 subtract 0111 set-less-than 1100 nor Arithmetic-17**Overflow**Decimal Binary Decimal 2’s complement 0 0000 0 0000 1 0001 -1 1111 2 0010 -2 1110 3 0011 -3 1101 4 0100 -4 1100 5 0101 -5 1011 6 0110 -6 1010 7 0111 -7 1001 -8 1000 Ex: 7 + 3 = 10 but ... - 4 - 5 = - 9 but … 0 1 1 1 1 0 0 0 0 1 1 1 7 1 1 0 0 -4 + 0 0 1 1 3 + 1 0 1 1 -5 1 0 1 0 -60 1 11 7 Arithmetic-18**Overflow Detection**• Overflow: result too big/small to represent • -8 4-bit binary number 7 • When adding operands with different signs, overflow cannot occur! • Overflow occurs when adding: • 2 positive numbers and the sum is negative • 2 negative numbers and the sum is positive => sign bit is set with the value of the result • Overflow if: Carry into MSB Carry out of MSB 0 1 1 1 1 0 0 0 0 1 1 1 7 1 1 0 0 -4 + 0 0 1 1 3 + 1 0 1 1 -5 1 0 1 0 -60 1 1 17 Arithmetic-19**Overflow Detection Logic**• Overflow = CarryIn[N-1] XOR CarryOut[N-1] CarryIn0 A0 1-bit ALU Result0 X Y X XOR Y B0 CarryOut0 0 0 0 CarryIn1 0 1 1 A1 1-bit ALU Result1 1 0 1 B1 CarryOut1 1 1 0 CarryIn2 A2 1-bit ALU Result2 B2 CarryIn3 Overflow A3 1-bit ALU Result3 B3 CarryOut3 Arithmetic-20**Dealing with Overflow**• Some languages (e.g., C) ignore overflow • Use MIPS addu, addui, subu instructions • Other languages (e.g., Ada, Fortran) require raising an exception • Use MIPS add, addi, sub instructions • On overflow, invoke exception handler • Save PC in exception program counter (EPC) register • Jump to predefined handler address • mfc0 (move from coprocessor reg) instruction can retrieve (copy) EPC value (to a general purpose register), to return after corrective action (by jump register instruction) Arithmetic-21**Zero Detection Logic**• Zero Detection Logic is a one BIG NOR gate (support conditional jump) CarryIn0 A0 Result0 1-bit ALU B0 CarryOut0 CarryIn1 A1 Result1 1-bit ALU B1 Zero CarryOut1 CarryIn2 A2 Result2 1-bit ALU B2 CarryOut2 CarryIn3 A3 Result3 1-bit ALU B3 CarryOut3 Arithmetic-22**Problems with Ripple Carry Adder**• Carry bit may have to propagate from LSB to MSB => worst case delay: N-stage delay CarryIn0 CarryIn A0 1-bit ALU Result0 B0 A CarryOut0 CarryIn1 A1 1-bit ALU Result1 B1 CarryOut1 CarryIn2 A2 1-bit ALU Result2 B B2 CarryOut CarryOut2 CarryIn3 Design Trick: look for parallelism and throw hardware at it A3 1-bit ALU Result3 B3 CarryOut3 Arithmetic-23**Carry Lookahead: Theory (I)(Appendix C)**• CarryOut=(B*CarryIn)+(A*CarryIn)+(A*B) • Cin2=Cout1= (B1 * Cin1)+(A1 * Cin1)+ (A1 * B1) • Cin1=Cout0= (B0 * Cin0)+(A0 * Cin0)+ (A0 * B0) • Substituting Cin1 into Cin2: • Cin2=(A1*A0*B0)+(A1*A0*Cin0)+(A1*B0*Cin0) +(B1*A0*B0)+(B1*A0*Cin0)+(B1*B0*Cin0) +(A1*B1) B1 B0 A1 A0 Cin1 Cin0 Cin2 1-bit ALU 1-bit ALU Cout1 Cout0 Arithmetic-24**Carry Lookahead: Theory (II)**• Now define two new terms: • Generate Carry at Bit i: gi = Ai * Bi • Propagate Carry via Bit i: pi = Ai xor Bi • We can rewrite: • Cin1=g0+(p0*Cin0) • Cin2=g1+(p1*g0)+(p1*p0*Cin0) • Cin3=g2+(p2*g1)+(p2*p1*g0)+(p2*p1*p0*Cin0) • Carry going into bit 3 is 1 if • We generate a carry at bit 2 (g2) • Or we generate a carry at bit 1 (g1) andbit 2 allows it to propagate (p2 * g1) • Or we generate a carry at bit 0 (g0) andbit 1 as well as bit 2 allows it to propagate ….. Arithmetic-25**A Plumbing Analogy for Carry Lookahead (1, 2, 4 bits)**Arithmetic-26**CarryIn0**A0 1-bit ALU Result0 B0 A1 1-bit ALU Result1 B1 A2 1-bit ALU Result2 B2 A3 1-bit ALU Result3 B3 CarryOut3 Carry Lookahead Adder • No Carry bit propagation from LSB to MSB Arithmetic-27**Common Carry Lookahead Adder**• Expensive to build a “full” carry lookahead adder • Just imagine length of the equation for Cin31 • Common practices: • Cascaded carry look-ahead adder • Multiple level carry look-ahead adder Arithmetic-28**A[31:24]**B[31:24] A[23:16] B[23:16] A[15:8] B[15:8] A[7:0] B[7:0] 8 8 8 8 8 8 8 8 8-bit Carry Lookahead Adder 8-bit Carry Lookahead Adder C24 C16 8-bit Carry Lookahead Adder 8-bit Carry Lookahead Adder C8 C0 8 8 8 8 Result[31:24] Result[23:16] Result[15:8] Result[7:0] Cascaded Carry Lookahead • Connects several N-bit lookahead adders to form a big one Arithmetic-29**Carry Lookahead Unit**cin cout 4 4 4 gi pi Example: Carry Lookahead Unit Arithmetic-30**Example: Cascaded Carry Lookahead**• Connects several N-bit lookahead adders to form a big one c12 c8 c4 c0 4-bit Carry Lookahead Unit 4-bit Carry Lookahead Unit 4-bit Carry Lookahead Unit 4-bit Carry Lookahead Unit p[15:12] g[15:12] p[11:8] g[11:8] p[7:4] g[7:4] p[3:0] g[3:0] c[4:1] c[8:5] c[12:9] c[16:13] + + + + + + + + + + + + + + + + Arithmetic-31**A[7:0]**B[7:0] 8 8 8-bit Carry Lookahead Adder C0 8 Result[7:0] Multiple Level Carry Lookahead • View an N-bit lookahead adder as a block • Where to get Cin of the block ? A[31:24] B[31:24] A[23:16] B[23:16] A[15:8] B[15:8] 8 8 8 8 8 8 C16 C8 C24 8-bit Carry Lookahead Adder 8-bit Carry Lookahead Adder 8-bit Carry Lookahead Adder 8 8 8 Result[31:24] Result[23:16] Result[15:8] • Generate “super” Pi and Gi of the block • Use next level carry lookahead structure to generate block Cin Arithmetic-32**A Plumbing Analogy for Carry Lookahead (Next Level P0 and**G0) Arithmetic-33**A Carry Lookahead Adder**A B Cout 0 0 0 kill 0 1 Cin propagate 1 0 Cin propagate 1 1 1 generate G = A * B P = A + B**P**G Carry Lookahead Unit cin cout 4 4 4 gi pi Example: Carry Lookahead Unit Arithmetic-35**P3, G3**P0, G0 P2, G2 P1, G1 Example: Multiple Level Carry Lookahead C[4:0] 4-bit Carry Lookahead Unit c12 c8 c4 c0 4-bit Carry Lookahead Unit 4-bit Carry Lookahead Unit 4-bit Carry Lookahead Unit 4-bit Carry Lookahead Unit p[15:12] g[15:12] p[11:8] g[11:8] p[7:4] g[7:4] p[3:0] g[3:0] c[4:1] c[8:5] c[12:9] c[16:13] + + + + + + + + + + + + + + + + + Arithmetic-36**Carry-select Adder**CP(2n) = 2*CP(n) n-bit adder n-bit adder CP(2n) = CP(n) + CP(mux) n-bit adder n-bit adder 0 n-bit adder 1 Design trick: guess Cout Arithmetic-37**Arithmetic for Multimedia**• Graphics and media processing operates on vectors of 8-bit and 16-bit data • Use 64-bit adder, with partitioned carry chain • Operate on 8×8-bit, 4×16-bit, or 2×32-bit vectors • SIMD (single-instruction, multiple-data) • Saturating operations • On overflow, result is largest representable value • c.f. 2s-complement modulo arithmetic • E.g., clipping in audio, saturation in video Arithmetic-38**Outline**• Addition and subtraction (Sec. 3.2) • Constructing an arithmetic logic unit (Appendix C) • Multiplication (Sec. 3.3, Appendix C) • Division (Sec. 3.4) • Floating point (Sec. 3.5) Arithmetic-39**$t3**00011111111111111111111111111111 $t4 11000000000000000000000000000000 Multiplication in MIPS mult $t1, $t2 # t1 * t2 • No destination register: product could be ~264; need two special registers to hold it • 3-step process: $t1 01111111111111111111111111111111 01000000000000000000000000000000 X $t2 00011111111111111111111111111111 11000000000000000000000000000000 Hi Lo mfhi $t3 mflo $t4 Arithmetic-41**MIPS Multiplication**• Two 32-bit registers for product • HI: most-significant 32 bits • LO: least-significant 32-bits • Instructions • mult rs, rt / multu rs, rt • 64-bit product in HI/LO • mfhi rd / mflo rd • Move from HI/LO to rd • Can test HI value to see if product overflows 32 bits • mul rd, rs, rt • Least-significant 32 bits of product –> rd Arithmetic-42**Unsigned Multiply**• Paper and pencil example (unsigned): Multiplicand 1000tenMultiplier X 1001ten 1000 0000 0000 1000 Product 01001000ten • m bits x n bits = m+n bit product • Binary makes it easy: • 0 => place 0 ( 0 x multiplicand) • 1 => place a copy ( 1 x multiplicand) • 2 versions of multiply hardware and algorithm Arithmetic-43**Unsigned Multiplier (Ver. 1)**• 64-bit multiplicand register (with 32-bit multiplicand at right half), 64-bit ALU, 64-bit product register, 32-bit multiplier register Arithmetic-44**Multiply Algorithm (Ver. 1)**Start Multiplier0 = 1 Multiplier0 = 0 1. Test Multiplier0 0010 x 0011 Product Multiplier Multiplicand 0000 0000 0011 0000 0010 0000 0010 0001 0000 0100 0000 0110 0000 0000 1000 0000 0110 0000 0001 0000 0000 0110 0000 0010 0000 1a. Add multiplicand to product and place the result in Product register 2. Shift Multiplicand register left 1 bit 3. Shift Multiplier register right 1 bit No: < 32 repetitions 32nd repetition? Yes: 32 repetitions Done**Observations: Multiply Ver. 1**• 1 clock per cycle => 100 clocks per multiply • Ratio of multiply to add 5:1 to 100:1 • Half of the bits in multiplicand always 0=> 64-bit adder is wasted • 0’s inserted in right of multiplicand as shifted=> least significant bits of product never changed once formed • Instead of shifting multiplicand to left, shift product to right? • Product register wastes space => combine Multiplier and Product register Arithmetic-46**Unsigned Multiply**• Paper and pencil example (unsigned): Multiplicand 1000tenMultiplier X 1001ten 1000 0000 0000 1000 Product 01001000ten • m bits x n bits = m+n bit product • Binary makes it easy: • 0 => place 0 ( 0 x multiplicand) • 1 => place a copy ( 1 x multiplicand) • 2 versions of multiply hardware and algorithm Arithmetic-47**Unisigned Multiplier (Ver. 2)**• 32-bit Multiplicand register, 32 -bit ALU, 64-bit Product register (HI & LO in MIPS), (0-bit Multiplier register) Arithmetic-48**1. Test**Product0 Multiply Algorithm (Ver. 2) Start Product0 = 1 Product0 = 0 Multiplicand Product0010 0000 0011 00100011 0010 00010001 00110001 0010 00011000 0010 00001100 0010 0000 0110 1a. Add multiplicand to left half of product and place the result in left half of Product register 2. Shift Product register right 1 bit 32nd repetition? No: < 32 repetitions Yes: 32 repetitions Done

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