CHAPTER 3 - PowerPoint PPT Presentation

chapter 3 n.
Skip this Video
Loading SlideShow in 5 Seconds..
CHAPTER 3 PowerPoint Presentation
play fullscreen
1 / 35
Download Presentation
Download Presentation


- - - - - - - - - - - - - - - - - - - - - - - - - - - E N D - - - - - - - - - - - - - - - - - - - - - - - - - - -
Presentation Transcript

  1. CHAPTER 3 Counter Application (Part B) By : Pn Siti Nor Diana Ismail

  2. ii. Cascade Counter • It connected in cascade to achieve higher modulus operation • Last stage output of one counter derive input of next counter • Also used to divide high frequency clock signal

  3. Example : 2-bit and 3-bit counter

  4. Based on 2 cascaded counter given. - Asynchronous counter have positive edge-triggered - all both JK input are high. So, output always toggle when clock triggered. - initial condition are LOW. • The final output modulus-8 counter (Q4) occurs once for every 32 input clock pulse. • So, it can be classified as divide-by-32 counter. • Therefore, the overall modulus 4x8=32

  5. When operating synchronous counter in cascaded configuration, it necessary to use count enable (CTEN) and terminal count (TC) function to achieve higher-modulus operation. • CTEN = G while TC = analog to ripple output (RCO). (for some devices)

  6. Example 1: A modulus-100 counter using cascaded decade counter

  7. This modulus-100 counter operation is :- - TC output counter1 connect to CTEN input counter2. - CTEN input on counter2 start from low until counter1 reach last or TC=high. - When TC=high, it will enable counter2. in this case, when 1st clock pulse after counter1 reach TC(CLK10) counter2 goes from initial state to 2nd state. - it will continuosly. Counter2 will complete one cycle after 100 clock pulses. - Since it decade counter, counter 1 must go through 10 complete cycles before counter 2 complete its 1st cycle. (Every 10 cycles of Counter 1, Counter 2 goes through 1 cycle). Counter 2 completes cycle after 100 clocks - overall modulus of 2 cascaded counter; 10 x 10 = 100

  8. Example 2 :3 cascaded decade counter Given basic clock frequency 1MHz to obtain 100kHz, 10kHz and 1kHz by using cascaded counter. (as a frequency divider)

  9. Also know as countdown chains Solution: • series of cascade decade counter can be formed. • If 1MHz signal divide by 10, so output = 100kHz • If 100kHz divide by 10, so output = 10kHz • If 10kHz divide by 10, output = 1kHz • So, we can used 3 cascade decade counter to produce 1kHz.

  10. Example 3 Determine the overall modulus of the two cascaded counter for (a) and (b) For (a) the overall modulus for the 3 counter configuration is 8 x 12 x 16 = 1536for (b) the overall modulus for the 4 counter configuration is 10 x 4 x 7 x 5 = 1400

  11. Example 4 : A divide-by-100 counter using two 74LS160 decade counters. Used 74162 decade counter to obtain 10kHz waveform 1MHz clock. Show a logic diagram.

  12. Solution; • to obtain 10kHz from 1MHz is required a division factor of 100. • So, the 2 logic ICs (74LS162) should cascaded.

  13. Exercise Show with general blocks diagram how to achieve each of the following using a FF, a decade counter and 4-bit binary counter or any combination • Divide by 20 counter • Divide by 32 counter • Divide by 160 counter • Divide by 320 counter

  14. iii. Counter Decoding • It ‘s necessary that some state to be decoded • By using decoder or logic gates • TC is a single decoded state (the last state) in counter sequence

  15. Example 1: Decoding of state 6 (110). To determine when the counter is in a certain states in its sequence by using decoders or logic gates.

  16. Solution : • when Q2=1, Q1=1 and Q0=0, a High appears on output decoding gate indicate counter is at State6. • It call active-HIGH decoding. • If replace AND-Gates with NAND-Gates, it will provide active-LOW decoding.

  17. Example 2 Implement the decoding of binary state2 and binary state7 of 3-bit synchronous counter. Show entire counter timing diagram and output waveform of decoding gates. Binary state2 = Q2’ Q1 Q0’ = (010). Binary state7 = Q2 Q1 Q0 = (111). A 3-bit counter with active-HIGH decoding of count2 and count7.

  18. Solution :

  19. Exercise • Show the logic for decoding state 5 in the 3-bit counter.

  20. Decoding Glitches • Propagation delay due to ripple effect in synchronous counter create transition state in which the counter output change at different times. • State produce voltage spike at short duration (glitches) on output decoder connect to counter. • Glitches problem also occurs to some degree with synchronous counter because propagation delay from clock to Q output each Flip-Flops.

  21. - Outputs with glitches from the previous decoder. - Glitch widths are exaggerated for illustration and are usually only a few nanoseconds wide.

  22. How to eliminate the GLITCHES? • Delay cause false state at short duration. • Value of false binary state at each critical transition is indicate on diagram. • One ways to eliminate “glitches”, - is to enable the decode output at time after “glitches” had time to disappear known as strobing.

  23. iv. Counter Application • Digital Clock. • Automobile Parking Control. • Parallel to Serial Data Conversion (MULTIPLEXING)

  24. Digital Clock • Logic diagram display second, minutes and hours. • 60Hz sinusoidal AC voltage connect to 60Hz pulse waveform and divide to 1Hz by using divide-by-60 (include divide-by-10 and divide-by-6). • Both second and minutes produce divide-by-60 counter and it will count from 0 to 59. • This digital clock use synchronous decade counter in implementation.

  25. Simplified logic diagram for a 12-hour digital clock.

  26. Continue in the next class

  27. Logic diagram of typical divide-by-60 counter using 74LS160A synchronous decade counters. Note that the outputs are in binary order (the right-most bit is the LSB).

  28. Digital Clock = hours definition • Hours counter implement with decade counter and flip-flops. • Initially both decade counter flip-flops = Reset. • Decode-12 and decode-9 output = High, so decade counter through all state from 0 to 9 and recycle from 9 to 0. • Flip-flops goes SET state (J=1, K=0) so it will illuminate (nyala) segment 1 on 10-hours display. • In state12, Q2 output decade counter is High, so flip-flops still SET and decode-12 gates output = LOW.

  29. Logic diagram for hours counter and decoders. Note that on the counter inputs and outputs, the right-most bit is the LSB.

  30. Automobile Parking Control = Counter Application • Use up/down counter to solve problem. • Monitor available space in the one-100 space parking garage and provide full condition by display sign and lower gate bar at entrance. • The system consist :- - opto-electronic sensor at entrance and exit garage. - up/down counter. - interface circuit use counter output to turn full-sign on/off and lower/raise gate bar at entrance.

  31. Functional block diagram for parking garage control.

  32. Logic diagram for modulus-100 up/down counter for automobile parking control.

  33. Automobile Parking Control = Definition • up/down use 2-cascade IC. • Counter initial preset to 0 by using parallel data input. • Each car enter garage break a light beam and activate sensor. Positive-pulse set SR latches on leading edge. • Low on Q’ output latches put counter UP mode. • Sensor pulse goes through NOR-Gates and clock the counter on LOW-to-HIGH transition. • When cars enter garage, counter increase by 1. • When count last stage (100 unit) the MAX/MIN = High and it activate light Full-Sign and low gate bar. • When car exit, sensor produce (positive pulse) which Reset SR latches and put counter DOWN mode. So, it will decrease. • If garage full and car leave, MAX/MIN = Low, so it will turning off Full-Sign and raising the bar gate.

  34. Parallel to Serial Data Conversion (MULTIPLEXING). = Counter Application • Parallel data bit on MUX input convert to serial data bit on single transmission line. • Parallel data = a group of bit appear on parallel line in time sequence. • Serial data = a group of bit appear on single line in time sequence. • Counter goes binary sequence from 0 to 7. - each bit start D0. - select and pass through MUX output line. - after 8 clock pulses, data byte has been convert to serial format and sent out transmission lines.

  35. Parallel-to-serial data conversion logic.