ECE 331 – Digital System Design

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Power Dissipation and Propagation Delay. ECE 331 – Digital System Design. Power Dissipation. Power Consumption. Each integrated circuit (IC) consumes power P T = P S + P D P T = total power consumed by IC P S = static or quiescent power consumption P D = dynamic power consumption.

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ECE 331 - Digital System DesignPower Consumption
• Each integrated circuit (IC) consumes power
• PT = PS + PD
• PT = total power consumed by IC
• PS = static or quiescent power consumption
• PD = dynamic power consumption
ECE 331 - Digital System DesignStatic Power Consumption
• PS = VCC * ICC
• VCC = supply voltage
• ICC = quiescent supply current
• PS = static power consumption
• ICC and VCC are specified in the datasheet for integrated circuit (IC).
• PS for CMOS devices is very small
ECE 331 - Digital System Design

Example:

Calculate the static power dissipation for a 74LS00 2-input NAND gate.

Static Power Consumption
ECE 331 - Digital System DesignExample: 74LS00 (TTL)
• Supply Voltage
• 4.75 V <= VCC <= 5.25 V
• Supply Current
• High Output: ICCmax = 1.6 mA
• Low Output: ICCmax = 4.4 mA
• Maximum static power consumption
• High Output: PS = 8.4 mW
• Low Output: PS = 23.1 mW
ECE 331 - Digital System DesignExample: 74LS00 (TTL)
• Example: (continued)
• Duty Cycle
• Clock signal typically has 50% duty cycle
• PS = PS_high * thigh + PS_low * tlow
• PS_high = 8.4 mW
• PS_low = 23.1 mW
• Assume 50% duty cycle (high / low half the time)
• PS = 8.4 mW * 0.5 + 23.1 mW * 0.5 = 15.8 mW
• Assume 60% duty cycle (high 60% of the time)
• PS = 8.4 mW * 0.6 + 23.1 mW * 0.4 = 14.28 mW
ECE 331 - Digital System Design

Example:

Compare the static power dissipation of the 74LS00 NAND gate with that of

the 74HC00 NAND gate.

Static Power Consumption
ECE 331 - Digital System DesignExample: 74HC00 (CMOS)
• PS = VCC * ICC
• Supply Voltage
• VCC = 6.0 V
• Supply Current
• ICC = 20 mA
• Maximum static power consumption
• PS = 6.0 V * 20 mA = 120 mW
ECE 331 - Digital System DesignDynamic Power Consumption
• TTL
• PD ~= 0 W
• CMOS
• PD != 0 W
• Movement of charge into and out of device capacitances is used to determine dynamic power consumption.
ECE 331 - Digital System DesignDynamic Power Consumption
• CMOS
• Charge is stored in the internal (CPD) and load (CL) capacitances
• CPD = power dissipation capacitance (internal)
• CL = capacitance of load and wires (external)
• Capacitances are in parallel
• CT = total capacitance = CPD + CL
• Stored charge (Q)
• QT = CT * VDD = (CPD + CL) * VDD
ECE 331 - Digital System DesignDynamic Power Consumption
• CMOS (continued)
• Charge is moved on each output transition
• Output transition from high to low and low to high
• Movement of charge = current
• IAVG = (CPD + CL) * VDD * fT
• fT = output frequency (i.e. # of transitions per second)
• PD = IAVG * VDD = (CPD + CL) * V2DD * fT
ECE 331 - Digital System Design

Example:

Calculate the dynamic power consumption for a 74HC00 2-input NAND gate.

Dynamic Power Consumption
ECE 331 - Digital System DesignDynamic Power Consumption
• Example: 74HC00 (Quad 2-input NAND)

VDD = 5 V, CPD = 22 pF, CL = 50 pF

PD = (22 pF + 50 pF) * (5 V)2 * fT

FT (Hz) PD

1K 1.8 W

1M 1.8 mW

100M 180 mW

IDDmax = 20 A

PS = VDD * IDDmax = 5 V * 20 A = 100 W

ECE 331 - Digital System DesignTotal Power Consumption
• PT = PS + PD
• Compare PT for Quad 2-input NAND (74xx00)

0 Hz 1 MHz 100 MHz

TTL 15.8 mW 15.8 mW 15.8 mW

CMOS 100 W 1.805 mW 180 mW

• Compare TTL and CMOS

TTL CMOS

PS VCC * ICC VDD * IDD

PD ~ 0 W (CPD + CL) * V2DD * fT

ECE 331 - Digital System DesignDefinitions
• Propagation Delay: The time from a change in one input to the final change in the output
• Maximum Delay: Worst-case delay
• Typical Delay: Mean delay
• Minimum Delay: Fastest possible
• The specifications for maximum, typical, and minimum delay are those measured by the manufacturer for the given conditions
ECE 331 - Digital System DesignPropagation Delay
• The time delay between a change in the input and the corresponding change in the output
• tPHL = time for output to transition from high to low
• tPLH = time for output to transition from low to high
• Ideal Propagation Delay

input

tPHL

tPLH

output

ECE 331 - Digital System Design

V

DD

input

50%

50%

Gnd

Propagation delay

Propagation delay

V

DD

90%

90%

output

50%

50%

Gnd

10%

10%

t

t

r

f

Propagation Delay
ECE 331 - Digital System DesignPropagation Delay
• Propagation delay is used to determine
• When outputs are valid
• The maximum speed of a combinational circuit
• The maximum frequency of a sequential circuit
ECE 331 - Digital System DesignSimple Analysis
• Given: A logic circuit with multiple inputs and a single output.
• Given: A single transition on one of the inputs.
• Determine: The time delay to propagate the transition on the input to the output.
• Use the propagation delay specified for each gate in the path between the input on which the transition occurred and the output.
• The gate propagation delays are specified in the associate datasheets.
ECE 331 - Digital System DesignMore Complex Analysis
• Problem: Some circuits have more than one path from an input to an output.
• Solution:
• Analyze every possible delay path

or

• Use the Worst Case Analysis
• Provides a conservative specification
• Often sufficient
ECE 331 - Digital System DesignMore Complex Analysis
• Problem: What if multiple inputs change at the same time?
• Solution:
• Analyze all combinations of input changes for all delay paths (to the output).

or

• Use the Worst Case Analysis
ECE 331 - Digital System DesignSum of Worst Cases (SWC) Analysis
• Write worst case delay next to each logic gate
• Select maximum of tPLH and tPHL
• Identify all input-output paths (i.e. all delay paths)
• Calculate worst case delay for each path
• Summarize in table
• Select worst case (i.e. maximum propagation delay)
ECE 331 - Digital System Design

Example:

Determine the worst-case propagation delay using the SWC Analysis for the XOR Logic Circuit.

ECE 331 - Digital System DesignExample

74F04

74LS08

74F32

f

74LS04

x

2

x

1

74F08

ECE 331 - Digital System DesignExample

74F04

74LS08

74F32

f

74LS04

x

2

x

1

TP = 32.1

74F08

ECE 331 - Digital System DesignExample

74F04

74LS08

74F32

f

74LS04

x

2

x

1

TP = 12.3

74F08

ECE 331 - Digital System DesignExample

74F04

74LS08

74F32

f

74LS04

x

2

x

1

TP = 26.1

74F08

ECE 331 - Digital System DesignExample

74F04

74LS08

74F32

f

74LS04

x

2

x

1

TP = 27.3

74F08

ECE 331 - Digital System DesignExample

Worst Case Propagation Delay = 32.1

ECE 331 - Digital System DesignSWC Analysis - Summary
• Permits Worst Case assessment of delay
• Simple / Robust
• Conservative
• If it does not satisfy the design requirements it may be necessary to implement a more detailed analysis.
• In particular, with the case-limiting paths