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Fundamentals of digital engineering l.jpg

Fundamentals of Digital Engineering:

Digital Logic

A Micro-Course

R. Katz

Grunt Engineer

Design Engineer (retired)

May 21, 2001


Abstract l.jpg
Abstract

The basics of Boolean algebra will be introduced, starting from simple combinational logic functions and basic sequential logic circuits such as latches and flip-flops. Based on these fundamentals, more complex logic structures such as decoders, adders, registers, and memories will constructed and their performance analyzed. FET Transistor basics will be reviewed and circuits introduced that demonstrate implementations of the basic logic elements in CMOS technology. The logic functions used as the architectural basis for programmable devices used in spaceborne electronics will be examined and analyzed.

Some common design problems found in flight circuits will be introduced.


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Micro-Course Outline

  • Introduction

  • Basic Logic

  • Hardware

  • Combinational Logic

  • Sequential Logic

  • Module Design in Programmable Devices



Logic values l.jpg
Logic Values

  • For binary hardware

    • Either a ‘1’ or a ‘0’

    • “Most of the time”

  • Other types of hardware can be have more than two values

  • Simulation can use a multi-value logic system

    • VHDL Std_Logic uses a nine-valued logic


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Binary Hardware Logic Values

  • Logic ‘1’

  • Logic ‘0’

  • Undefined value


Ttl logic levels l.jpg
TTL Logic Levels

  • Logic ‘1’ threshold - VIH

     2.0 V

  • Logic ‘0’ threshold - VIL

     0.8 V

  • Undefined

    0.8 V < v < 2.0 V


Ttl logic levels examples of undefined values l.jpg

Logic ‘1’

2.0V

Undefined

0.8V

Logic ‘0’

TTL Logic LevelsExamples of Undefined Values

  • Floating signals may take on illegal values

  • What happens during a signal transition?


Mil std 1553 l.jpg
MIL-STD-1553

  • Three physical values

    > +VTH

    < - VTH

    -VTH < v < +VTH

  • All values have meaning in MIL-STD-1553


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Intel Flash Memory

  • Intel® StrataFlash™ memory components store two bits per cell for high density and low cost.1

  • Smaller margins for radiation.

1http://www.intel.com/design/flcomp/prodbref/298044.htm


Physical logic values l.jpg
Physical Logic Values

  • Magnetic field (core memory, plated wire)

  • Voltage (static CMOS logic)

  • Charge (DRAM)

  • Position (contacts open/closed)

  • Frequency of Sound (tones for a modem)

  • Light (fiber optics - MIL-STD-1773)

  • Etc.



Logic values13 l.jpg
Logic Values

  • Levels

    • '0' or '1'

  • Pulses

    • Presence or absence of pulses

    • Pulse widths

    • Number of pulses

  • Zero crossings


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Switching Algebra

  • Two-valued variable from {0,1}

  • Two binary operations

    • AND ( • )

    • OR ( + )

  • One unary operation

    • NOT (  )


A multi valued logic system used in vhdl simulation l.jpg
A Multi-valued Logic SystemUsed In VHDL Simulation

TYPE std_ulogic IS (

‘U’, -- Uninitialized

‘X’, -- Forcing Unknown

‘0’, -- Forcing 0

‘1’, -- Forcing 1

‘Z’, -- High Impedance

‘W’, -- Weak Unknown

‘L’, -- Weak ‘0’

‘H’, -- Weak ‘1’

‘-’ -- Don’t Care

);


Unary operation not l.jpg

A Y

0 1

1 0

Unary Operation - NOT


Binary operation and l.jpg

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

Binary Operation - AND


Binary operation inclusive or l.jpg

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

Binary Operation - [Inclusive] OR


Binary functions l.jpg
Binary Functions

  • How many functions are there of two binary variables?

    • Basic combinatorics

    • 4 positions or rows: 00, 01, 10, 11

    • For each position you can select one of two values {0, 1}

    • Order counts since it is a function

    • Number of functions = 2 x 2 x 2 x 2 = 24 = 16


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Binary Functions - cont’d

  • How many functions are there of n binary variables?

    • 2n positions or rows

      • for n = 2: 00, 01, 10, 11

      • for n = 3: 000, 001, 010, 011, 100, 101, 110, 111

    • For each position or row you can select one of two values {0, 1}

    • Number of functions = 2^2n

      • for n = 2: 22 = 4; 2 x 2 x 2 x 2 = 24 = 16

      • for n = 3: 23 = 8; 2 x 2 x 2 x 2 x 2 x 2 x 2 x 2 = 28 = 64

      • for n = 4: 24 = 16; 216 = 65536


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Fan-In

  • Number of inputs to a logic gate

  • Examples for AND function

    • n = 2: Y = A • B

    • n = 3: Y = A • B • C

    • n = 4: Y = A • B • C • D


Logic functions l.jpg
Logic Functions

  • Any logic function can be implemented with AND, OR, and NOT.

  • One standard form is the sum of products

    • Example: Y = (A • B + C • D)

Inputs AND gates OR gates Inverters Outputs



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Universal Logic GateIntroduction

  • Some other logic functions

    • NOR ::= Negative OR

      Y = ( A + B )´

    • NAND ::= Negative AND

      Y = ( A • B )´

    • Multiplexor

      Y = A • S + B • S´

    • Look up table (LUT)

      Small memory


Universal logic gate nor function l.jpg
Universal Logic GateNOR Function

  • NOR ::= Negative OR

    Y = ( A + B )´

NOT

AND

OR


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Universal Logic GateNAND Function

  • NAND ::= Negative AND

    Y = ( A • B )´

NOT

AND

OR


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Universal Logic GateMultiplexor Function

  • Multiplexor

    Y = A • S + B • S´

OR

AND

NOT


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Universal Logic Gate Look up table (LUT)

  • Look up table (LUT)

    Small memory

NOT OR AND

A X Y A B Y A B Y

0 0 1 0 0 0 0 0 0

0 1 1 0 1 1 0 1 0

1 0 0 1 0 1 1 0 0

1 1 0 1 1 1 1 1 1


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Logic Assignments and Duality

Logic Gate - Positive Logic

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

0 = 0V

1 = 5V

Logic Gate and Voltage

A B Y

0V 0V 0V

0V 5V 0V

5V 0V 0V

5V 5V 5V

Logic Gate - Negative Logic

A B Y

1 1 1

1 0 1

0 1 1

0 0 0

1 = 0V

0 = 5V

Logic Gate - Negative Logic

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

1 = 0V

0 = 5V

Reorder Rows



Half adder l.jpg

Truth Table

x y C S

0 0 0 0

0 1 0 1

1 0 0 1

1 1 1 0

Half-Adder

Logic Equations

C = x • y

S = x  y

Schematic


Full adder l.jpg

Truth Table

x y z C S

0 0 0 0 0

0 0 1 0 1

0 1 0 0 1

0 1 1 1 0

1 0 0 0 1

1 0 1 1 0

1 1 0 1 0

1 1 1 1 1

Full-Adder

Logic Equations

C = x’yz + xy’z + xyz’ + xyz

= z • (x’y+xy’) + xy • (z+z’)

= z • (x  y) + x • y

= MAJ (x,y,z)

S = x’y’z + x’yz’ + xy’z’ + xyz

= x’yz’ + xy’z’ + x’y’z + xyz

= z’(x’y + xy’) + z(x’y’ + xy)

= z’(x  y) + z(x  y)’

= (x  y)  z

= x  y  z



Adding two numbers l.jpg
Adding Two Numbers

  • Many Types of Adders: Some examples:

  • Bit Serial Adder

    • Add time = n x f

  • Cascade Stages

    • Ripple carry adder

    • Add time = n x tPD

  • Carry Look Ahead Adder

    • Generate carries in parallel

    • e.g., 4-bit AM2902. Can have “look ahead” of the “look ahead” units.




Sample cla timing analysis l.jpg
Sample CLA Timing Analysis

  • Generate g and p: 1 gate delay

  • Generate C: 2 gate delays

  • Generate sum: 3 gate delays

  • Total: 6 gate delays

  • Total is independent of word length


Negative numbers and subtraction l.jpg
Negative Numbers and Subtraction

  • Several different codes for negative numbers

    • 2's complement

    • 1's complement

    • signed magnitude

    • others

  • For 2's complement, subtraction is implemented with the same hardware by negating the subtrahend. This is done by inverting each bit and adding one. The one can be added by setting the carry-in to the first stage equal to 1, saving an operation.



Transistor definitions l.jpg
Transistor Definitions

  • MOS - Metal Oxide Semiconductor

  • FET - Field Effect Transistor

  • BJT - Bipolar Junction Transistor


Mosfet and bjt l.jpg
MOSFET and BJT

drain

collector

body

base

gate

source

emitter

npn bipolar transistor

n-channel MOSFET



Bjt symbols l.jpg

collector

collector

base

base

emitter

emitter

BJT Symbols

pnp bipolar transistor

npn bipolar transistor


Mosfet symbols l.jpg
MOSFET Symbols

A circle is sometimes

used on the gate terminal

to show active low input




Basic cmos logic technology l.jpg
Basic CMOS Logic Technology

  • Based on the fundamental inverter circuit

  • Transistors (two) are enhancement-mode MOSFETs

    • N-channel with its source grounded

    • P-channel with its source connected to +V

  • Input: gates connected together

  • Output: drains connected


Cmos inverter l.jpg

VDD

p

A

Y = A'

n

GND

CMOS Inverter


Cmos inverter operation l.jpg
CMOS Inverter - Operation

Since the gate is essentially an open circuit it draws no current, and the output voltage will be equal to either ground or to the power supply voltage, depending on which transistor is conducting.

When input A is grounded (logic 0), the N-channel MOSFET is unbiased, and therefore has no channel enhanced within itself. It is an open circuit, and therefore leaves the output line disconnected from ground. At the same time, the P-channel MOSFET is forward biased, so it has a channel enhanced within itself, connecting the output line to the +Vsupply. This pulls the output up to +V (logic 1).

When input A is at +V (logic 1), the P-channel MOSFET is off and the N-channel MOSFET is on, thus pulling the output down to ground (logic 0). Thus, this circuit correctly performs logic inversion, and at the same time provides active pull-up and pull-down, according to the output state.



Cmos 2 input nor operation l.jpg
CMOS 2-Input NOR - Operation

This basic CMOS inverter can be expanded into NOR and NAND structures by combining inverters in a partially series, partially parallel structure. A practical example of a CMOS 2-input NOR gate is shown in the figure.

In this circuit, if both inputs are low, both P-channel MOSFETs will be turned on, thus providing a connection to +V. Both N-channel MOSFETs will be off, so there will be no ground connection. However, if either input goes high, that P-channel MOSFET will turn off and disconnect the output from +V, while that N-channel MOSFET will turn on, thus grounding the output.

Note the two p-channel FETs in series.



Cmos 2 input nand operation l.jpg
CMOS 2-Input NAND - Operation

A two-input NAND gate: a logic 0 at either input will force the output to logic 1; both inputs at logic 1 will force the output to go to logic 0.

Note the two n-channel FETs in series and the two p-channel FETs in parallel.

The pull-up and pull-down resistances at the output are never the same, and can change significantly as the inputs change state, even if the output does not change logic states. The result is uneven and unpredictable rise and fall times for the output signal. This problem was addressed, and was solved with the buffered, or B-series CMOS gates.



Cmos 2 input nand buffered55 l.jpg
CMOS 2-Input NAND: Buffered

The technique here is to follow the actual NAND gate with a pair of inverters. Thus, the output will always be driven by a single transistor, either P-channel or N-channel. Since they are as closely matched as possible, the output resistance of the gate will always be the same, and signal behavior is therefore more predictable. Typically, the p-channel transistor is approximately twice as wide as the n-channel transistor, because of the difference in conductivity between electronics and holes.

Note that we have not gone into all of the details of CMOS gate construction here. For example, to avoid damage caused by static electricity, different manufacturers developed a number of input protection circuits, to prevent input voltages from becoming too high. However, these protection circuits do not affect the logical behavior of the gates, so we will not go into the details here. This is not strictly true for most CMOS devices for applications that are power-switched; special inputs are required for power-off isolation between circuits.



Decoder fundamentals l.jpg
Decoder Fundamentals

  • Route data to one specific output line.

  • Selection of devices, resources

  • Code conversions.

  • Arbitrary switching functions

    • implements the AND plane

  • Asserts one-of-many signal; at most one output will be asserted for any input combination


Encoding l.jpg
Encoding

Binary

Decimal Unencoded Encoded

0 0001 00

1 0010 01

2 0100 10

3 1000 11

Note: Finite state machines may be unencoded ("one-hot")

or binary encoded. If the all 0's state is used, then

one less bit is needed and it is called modified

one-hot coding.


Why encode a logarithmic relationship l.jpg
Why Encode?A Logarithmic Relationship


2 4 decoder l.jpg

1 1

1 0

0 1

00

2:4 Decoder

What happens when the inputs goes from 01 to 10?


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2:4 Decoder with Enable

1 1

1 0

0 1

00



Static hazard l.jpg
Static Hazard

2:1 Mux implemented by

minimized Sum-of-Products

Idealized matched delays


Static hazard64 l.jpg
Static Hazard

In real circuits, delays don't

exactly match; Added delay

for illustration


Static hazard65 l.jpg

We now have a "glitch."

Static Hazard

Same waveform, zoomed in.


Static hazard66 l.jpg
Static Hazard

A B

1 1

1 0

0 1

0 0

0

1

1

0

S=0

S=1

1

0

1

0

Illustrating the minimized function on a Karnaugh map.

Only two 2-input AND gates are needed for the product terms


Static hazard67 l.jpg
Static Hazard

A B

1 1

1 0

0 1

0 0

0

1

1

0

S=0

S=1

1

0

1

0

The blue oval shows the redundant term used to cover the

transition between product terms.


Static hazard68 l.jpg
Static Hazard

How can we verify the

presence and operation

of the ‘redundant’ gate?


Static hazard69 l.jpg

0000 0

0001 1

0010 2

0011 3

0100 4

0101 5

0110 6

0111 7

1000 8

1001 9

1010 10

1011 11

1100 12

1101 13

1110 14

1111 15

0000 16

Static Hazard

Terminal count of

a 4-bit synchronous

counter.


Static hazard flight design example l.jpg
Static HazardFlight Design Example

TMR Triplet Majority Voter

High-skew buffer


Static hazard flight design example71 l.jpg
Static HazardFlight Design Example

Care is needed when using TMR circuits. First, the output of the voter may be susceptible to a logic hazard “glitch.” This is not a problem if the TMR is feeding the input of another synchronous input. However, the TMR output should never feed asynchronous inputs such as flip-flop clocks, clears, sets, read/write inputs, etc.

“Design Techniques for Radiation-Hardened FPGAs”

Actel Corporation, September 1997

-- based on “SEU Hardening of Field Programmable Gate Arrays (FPGAs) for Space

Applications and Device Characterization,” R. Katz, R. Barto, et. al., IEEE Transactions

on Nuclear Science, Dec. 1994.


Static hazard72 l.jpg
Static Hazard

We have covered static hazards. There are also dynamic hazards. An example of a dynamic hazard would be when a circuit is supposed to switch as follows:

0  1

But instead switches:

0  1  0  1

Any circuit that is static hazard free is also dynamic hazard free.


Common output stage definitions l.jpg
Common Output Stage Definitions

  • VOH - Output voltage when driving high

  • VOL - Output voltage when driving low

  • IOH - Output current when driving high

  • IOL - Output current when driving low

  • tT - Transition time, usually measured between 10% and 90% of the waveform (2.2)


V oh test configuration l.jpg
VOH Test Configuration

VCC

Output Stage

+

Programmable

Load

i

-


V ol test configuration l.jpg
VOL Test Configuration

VCC

Output Stage

+

VCC

Programmable

Load

i

-


A1460a tid v oh test post irradiation l.jpg
A1460A TID (VOH) TestPost-Irradiation


Slide77 l.jpg

A1460A TID (VOL) TestPost-Irradiation


Slide78 l.jpg

RT54SX32 TID (VOH) TestPost-Irradiation


Slide79 l.jpg

RT54SX32 TID (VOL) TestPost-Irradiation




Common interface levels l.jpg
Common Interface Levels

  • TTL

  • 5V CMOS

  • 5V PCI

  • 3.3V PCI

  • LVDS

  • LVTTL


Ttl voltage specification l.jpg
TTL Voltage Specification

  • VOH - 2.4 V

  • VOL - 0.5 V

  • VIH - 2.0 V

  • VIL - 0.8 V

  • '1' Noise margin = 400 mV

  • '0' Noise margin = 300 mV


5v cmos voltages l.jpg
5V CMOS Voltages

  • VOH - ~VDD (no DC load)

  • VOL - ~GND (No DC load)

  • VIH - 70% VDD

  • VIL - 30% VDD

  • Very high noise margin.



Basic rs flip flop nand l.jpg
Basic RS Flip-Flop (NAND)

A flip-flop holds 1 "bit".

"Bit" ::= "binary digit."


Clocked d flip flop l.jpg
Clocked D Flip-Flop

The present state is held when CP is low.


Clock pulse definition l.jpg

Negative Pulse

Positive Pulse

Positive

Edge

Negative

Edge

Negative

Edge

Positive

Edge

Clock Pulse Definition

Edges can also be referred to as leading and trailing.



Flip flop on rt54sx a not hardened l.jpg

Master Slave

Flip-Flop on RT54SX-A(Not hardened)



Rt54sx s latch seu hardened l.jpg
RT54SX-S Latch(SEU Hardened)


Flip flop timing rt54sx s l.jpg

Worst-case Military Conditions, VCCA=2.3, VCCI=3.0V, TJ=125C

-1 Speed Grade

Min Max Units

tRCO Sequential Clock-to-Q 1.0 ns

tCLR Asynchronous Clear-to-Q 0.9 ns

tPRESET Asynchronous Preset-to-Q 1.0 ns

tSUD Flip-Flop Data Input Set-Up 0.6 ns

tHD Flip-Flop Data Input Hold 0.0 ns

tWASYN Asynchronous Pulse Width 1.8 ns

Flip-Flop Timing: RT54SX-S


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Metastability - Introduction

  • Can occur if the setup, hold time, or clock pulse width of a flip-flop is not met.

  • A problem for asynchronous systems or events.

  • Can be a problem in synchronous systems.

  • Three possible symptoms:

    • Increased CLK -> Q delay.

    • Output a non-logic level

    • Output switching and then returning to its original state.

  • Theoretically, the amount of time a device stays in the metastable state may be infinite.

  • Many designers are not aware of metastability.


Slide95 l.jpg

Metastability

  • In practical circuits, there is sufficient noise to move the device output of the metastable state and into one of the two legal ones. This time can not be bound. It is statistical.

  • Factors that affect a flip-flop's metastable "performance" include the circuit design and the process the device is fabricated on.

  • The resolution time is not linear with increased circuit time and the MTBF is an exponential function of the available slack time.


Slide96 l.jpg

Metastability - Calculation

  • MTBF = eK2*t / ( K1 x FCLK x FDATA)

    t is the slack time available for settling

    K1 and K2 are constants that are characteristic of the flip-flop

    Fclock and Fdata are the frequency of the synchronizing clock and asynchronous data.

  • Software is available to automate the calculations with built-in tables of parameters.

  • Not all manufacturers provide data.




Metastable state possible output from a flip flop l.jpg
Metastable State:Possible Output from a Flip-flop


Metastable state possible outputs from a flip flop l.jpg
Metastable State:Possible Outputs from a Flip-flop

Correct Output





Register files simplified l.jpg

Register 2

Q

D

Register 1

CLK

Address - log2(num registers)

Register Files (Simplified)

D and Q are both sets of lines, with the number of lines

equal to the width of each register. There are often multiple

address ports, as well as additional data ports.



Slide106 l.jpg

Decoder

(AND plane)

MagneticCoreMemory

Register

Sense wires serve as OR plane.


Slide107 l.jpg

SemiconductorMemory

Decoder

(AND plane)

OR plane


Slide108 l.jpg

Rad-Hard PROM Architecture

No latches in this architecture


W28c64 eeprom simplified block diagram l.jpg

E2

Memory

Array

Edge

Detect &

Latches

Row

AddressDecoder

Column

AddressDecoder

Row

AddressLatches

Column

AddressLatches

64 Byte

Page

Buffer

Control

Latch

Control

Logic

Timer

I/O Buffer/

Data Polling

W28C64 EEPROMSimplified Block Diagram

A6-12

A0-5

CE*

WE*

Latch Enable

OE*

CLK

VW

I/O0-7

PE

RSTB


Module design of pals and fpgas l.jpg

Module Design of PALs and FPGAs


Programmable logic components l.jpg

AND

Plane

OR

Plane

Flip-Flops (optional)

Inputs + Buffers/Inverters

Inverters + Outputs

Programmable Logic Components

PROMs, PALs, and PLAs all have a similar architecture


Pal architecture l.jpg
PAL Architecture

Programmable AND plane and

fixed OR plane.

PALs have a built-in POR circuit to initialize all registers to zero.


Fpga logic modules l.jpg
FPGA Logic Modules

  • Actel (Act 1,2,3, SX)

    • Basics

    • Flip-flop Construction

  • UTMC/Quicklogic (i.e., UT4090)

    • RAM blocks

  • Xilinx (i.e., CQR40xxXL, Virtex)

    • LUTs/RAM

    • Carry Logic/Chain

  • Mission Research Corp. (MRC) - Orion

  • Atmel - AT6010


Act 2 logic module c mod l.jpg
Act 2 Logic Module: C-Mod

8-Input Combinational function

766 possible combinational

macros1

1”Antifuse Field Programmable Gate Arrays,” J. Greene, E. Hamdy, and S. Beal,

Proceedings of the IEEE, Vol. 91, No. 7, July 1993, pp. 1042-1056


Slide115 l.jpg

Act 2 Flip-flop Implementation

Feedback goes through

antifuses (R) and routing

segments (C)

Hard-wired Flip-flop

Routed or “C-C Flip-flop”




Ut4090 logic module l.jpg
UT4090 Logic Module

  • Antifuse Configuration Memory

  • Mux-based

  • Multiple Outputs

  • Wide logic functions


Ut4090 ram module l.jpg
UT4090 RAM Module

  • Dual-port

  • 1152 bits per cell

  • Four configurations

    • 64 X 18

    • 128 X 9

    • 256 X 4

    • 512 X 2

RE

WA(8:0)

WD(17:0)

RCLK

RA(8:0)

WE

WCLK

RD(17:0)

ASYNCRD

MODE(1:0)


Xc4000 series clb simplified clb carry logic not shown l.jpg
XC4000 Series CLBSimplified CLB - Carry Logic Not Shown

RAM LUTs

for Logic or

small SRAM

Two Flip-flops


Xqr4000xl carry path l.jpg
XQR4000XL Carry Path

Placement is important for performance.

General interconnect


Carry logic operation l.jpg
Carry Logic Operation

Effective Carry Logic for a Typical Addition - XQR4000XL



At60xx logic module l.jpg
AT60xx Logic Module

28 unique functions


At60xx logic module a closer look l.jpg
AT60xx Logic ModuleA Closer Look


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