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Digital Design: Principles and Practices

Digital Design: Principles and Practices. Chapter 6 Combinational Logic Design Practices. Introduction. If you are contemplating a career in digital design, it is recommended that you study the examples at least for Verilog or VHDL.

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Digital Design: Principles and Practices

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  1. Digital Design:Principles and Practices Chapter 6 Combinational Logic Design Practices

  2. Introduction • If you are contemplating a career in digital design, it is recommended that you study the examples at least for Verilog or VHDL. • A practical combinational circuit may have dozens of inputs and outputs and could require millions of terms to describe as an SOP expression, and billions of rows to describe in a truth table. • A complex circuit or system is conceived as a collection of smaller subsystems, each of which has a much simpler description.

  3. Introduction (cont’d) • Basic combinational building blocks discussed in this chapter: • Decoders • Encoders • Three-State Devices • Multiplexers (MUX) • XORs • Comparators • Adders & Subtractors • Multipliers

  4. 6.4 Decoders(including 6.4.1 – 6.4.4)

  5. Decoder • A decoder is a multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs, where the input and output codes are different. • The input code generally has fewer bits than the output code, and there is a one-to-one mapping from input code words into output code words. • In a one-to-one mapping, each input code word produces a different output code word. • The most common decoder circuit is an n-to-2ndecoder or binary decoder.

  6. A 2-to-4 (Binary) Decoder Figure 6-32 Table 6-4

  7. A 2-to-4 (Binary) Decoder – VerilogStructural-style Verilog Module Table V6-20 Structural-style Verilog module for the decoder in Figure 6-32.

  8. Decoder Circuit Structure

  9. A 3-to-8 Binary Decoder for Gray Code

  10. A Mechanical Encoding DiskUsing a 3-bit Gray Code

  11. A 3-to-8 Binary Decoder for Gray Code

  12. LogicDiagram Decoder • Truth table for a 4-bit (4-to-16) Decoder with Active-LOW outputs

  13. TruthTable Decoder • 4-bit decoder • Binary inputs • Active-low outputs

  14. BCD-to-Decimal Decoder

  15. LogicDiagram BCD-to-7-Segment Decoder

  16. TruthTable BCD-to-7-Segment Decoder

  17. 7-Segment Display LED (Light –Emitting Diode)

  18. 74x138 – Logic Symbol • 3-to-8 decoder • All of the output pins are active low.

  19. 74x138 – Truth Table

  20. 74x138 - Logic Diagram

  21. 74x138 – Different Logic Symbols

  22. Cascading Binary Decoder5-to-32 Decoder Using 74x138s

  23. 74x138-like 3-to-8 Binary DecoderBehavior-Style Verilog Module

  24. 74x138 – Logic Symbol • 3-to-8 decoder • All of the output pins are active low.

  25. 6.5 Encoders(including 6.5.1 & 6.5.2)

  26. Encoder • An encoder is a combinational logic circuit that essentially performs a “reverse” decoder function. • An encoder’s input code normally has more bits than its output code, whereas a decoder’s output code normally has more bits than its input code. • Probably the simplest encoder to build is a 2n-to-nencoder or binary encoder.

  27. 8-to-3 (Binary) Encoder Y0 = I1 + I3 + I5 + I7 Y1 = I2 + I3 + I6 + I7 Y2 = I4 + I5 + I6 + I7

  28. 8-to-3 (Binary) Encoder- Truth Table

  29. A Request Encoder

  30. Priority Encoder • Input I7 has the highest priority. • The IDLE output is asserted if no inputs are asserted.

  31. Decimal-to-BCD Encoder

  32. Decimal-to-BCD Encoder • A3 = 8 + 9 • A2 = 4 + 5 + 6 + 7 • A1 = 2 + 3 + 6 + 7 • A0 = 1 + 3 + 5 + 7 + 9

  33. Decimal-to-BCD Encoder • A3 = 8 + 9 • A2 = 4 + 5 + 6 + 7 • A1 = 2 + 3 + 6 + 7 • A0 = 1 + 3 + 5 + 7 + 9 Basic logic diagram of a decimal-to-BCD encoder

  34. 8-to-3 Encoder

  35. 74x148 – Logic Symbol • 8-input priority encoder • All inputs and outputs are active low. • EI_L : enable input • GS_L : group select (got something) • EO_L : enable output (used for cascading). EO_L is asserted if EI_L is asserted but no request input is asserted.

  36. 74x148 – Truth Table

  37. 74x148-like 8-input Priority Encoder Behavior-Style Verilog Module

  38. 6.6 Three-State Devices(including 6.6.1)

  39. Three-State Devices • Three states: 0, 1, or Hi-Z • Hi-Z: High Impedance

  40. Tristate Inverter Implementation of an Tristate Inverter

  41. Eight Sources Sharing a Three-State Party Line

  42. 74x541: Octal Three-State Buffer

  43. 74x541-like Three-State Device Behavior-Style Verilog Module

  44. 6.7 Multiplexers(including 6.7.1)

  45. Multiplexer (MUX) • A multiplexer is a digital switch – it connects data from one of n sources to its output. • Figure 6-57(a) • n sources of data • each source is b bits wide • b output bits • usually, 2s = n • enable signal (EN) • A Multiplexer is often called a MUX for short. Figure 6-57 (a)

  46. Multiplexer (MUX)

  47. 75x151: 8-input 1-bit MUX

  48. 75x151: 8-input 1-bit MUX

  49. 74x157: 2-input 4-bit MUX

  50. 74x157 2-input 4-bit MUX

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